PIC24FJ256GA106T-I Datasheet, PDF (156/292 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
13.2 Compare Operations
In Compare mode (Figure 13-1), the enhanced output
compare module can be configured for single-shot or
continuous pulse generation; it can also repeatedly
toggle an output pin on each timer event.
To set up the module for compare operations:
1. Configure the OCx output for one of the
available Peripheral Pin Select pins.
2. Calculate the required values for the OCxR and
(for Double Compare modes) OCxRS duty cycle
registers:
a) Determine the instruction clock cycle time.
Take into account the frequency of the
external clock to the timer source (if one is
used) and the timer prescaler settings.
b) Calculate time to the rising edge of the out-
put pulse relative to the timer start value
(0000h).
c) Calculate the time to the falling edge of the
pulse based on the desired pulse width and
the time to the rising edge of the pulse.
3. Write the rising edge value to OCxR, and the
falling edge value to OCxRS.
4. Set the Timer Period register, PRy, to a value
equal to or greater than the value in OCxRS.
5. Set the OCM2:OCM0 bits for the appropriate
compare operation (= 0xx).
6. For Trigger mode operations, set OCTRIG to
enable Trigger mode. Set or clear TRIGMODE to
configure trigger operation, and TRIGSTAT to
select a hardware or software trigger. For
Synchronous mode, clear OCTRIG.
7. Set the SYNCSEL4:SYNCSEL0 bits to configure
the trigger or synchronization source. If
free-running timer operation is required, set the
SYNCSEL bits to ‘00000’ (no sync/trigger
source).
8. Select the time base source with the
OCTSEL2:OCTSEL0 bits. If necessary, set the
TON bit for the selected timer which enables the
compare time base to count. Synchronous mode
operation starts as soon as the time base is
enabled; Trigger mode operation starts after a
trigger source event occurs.
FIGURE 13-1:
OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE)
OCTSELx
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
OC Clock
Sources
Trigger and
Sync Sources
Clock
Select
Increment
Reset
Trigger and
Sync Logic
Match Event
Reset
OCxCON1
OCxCON2
OCxR
Comparator
Match Event
OCMx
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLT0
OCFLT0
OCxTMR
Comparator
Match Event
OC Output and
Fault Logic
OCxRS
OCx Pin⁽¹⁾
OCFA/OCFB
OCx Interrupt
Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral
Pin Select” for more information.
DS39905B-page 154
Preliminary
© 2008 Microchip Technology Inc.