PIC24FV32KA304_1 Datasheet, PDF (215/320 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0
U-0
R/W-0
U-0
U-0
ADON
—
ADSIDL
—
—
bit 15
r-0
R/W-0
R/W-0
—
FORM1
FORM0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SSRC3
SSRC2
SSRC1
SSRC0
—
bit 7
R/W-0
ASAM
R/W-0 HSC
SAMP
R/C-0 HSC
DONE
bit 0
Legend:
C = Clearable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
r = Reserved bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9-8
bit 7-4
bit 3
bit 2
bit 1
bit 0
ADON: A/D Operating Mode bit
1 = A/D Converter module is operating
0 = A/D Converter is off
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘1’
FORM<1:0>: Data Output Format bits (see formats following)
11 = Fractional result, signed, left-justified
10 = Absolute fractional result, unsigned, left-justified
01 = Decimal result, signed, right-justified
00 = Absolute decimal result, unsigned, right-justified
SSRC<3:0>: Sample Clock Source Select bits
1111 = Not available; do not use



1000 = Not available; do not use
0111 = Internal counter ends sampling and starts conversion (auto-convert)
0110 = Not Available; do not use
0101 = Timer1 event ends sampling and starts conversion
0100 = CTMU event ends sampling and starts conversion
0011 = Timer5 event ends sampling and starts conversion
0010 = Timer3 event ends sampling and starts conversion
0001 = INT0 event ends sampling and starts conversion
0000 = Clearing the SAMP bit in software ends sampling and begins conversion
Unimplemented: Read as ‘0’
ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after last conversion; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is manually set
SAMP: A/D Sample Enable bit
1 = A/D Sample-and-Hold amplifiers are sampling
0 = A/D Sample-and-Hold are holding
DONE: A/D Conversion Status bit
1 = A/D conversion cycle is completed
0 = A/D conversion cycle is not started or in progress
 2011 Microchip Technology Inc.
DS39995B-page 215