PIC24FV32KA304_1 Datasheet, PDF (158/320 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
15.3 Pulse-Width Modulation (PWM)
Mode
In PWM mode, the output compare module can be
configured for edge-aligned or center-aligned pulse
waveform generation. All PWM operations are
double-buffered (buffer registers are internal to the
module and are not mapped into SFR space).
To configure the output compare module for
edge-aligned PWM operation:
1. Calculate the desired on-time and load it into the
OCxR register.
2. Calculate the desired period and load it into the
OCxRS register.
3. Select the current OCx as the synchronization
source by writing 0x1F to SYNCSEL<4:0>
(OCxCON2<4:0>) and ‘0’ to OCTRIG
(OCxCON2<7>).
4. Select a clock source by writing the
OCTSEL2<2:0> (OCxCON<12:10>) bits.
5. Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin utilization.
6. Select the desired PWM mode in the OCM<2:0>
(OCxCON1<2:0>) bits.
7. If a timer is selected as a clock source, set the
TMRy prescale value and enable the time base by
setting the TON (TxCON<15>) bit.
FIGURE 15-2:
OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE)
OCTSELx
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
OCxCON1
OCxCON2
OCxR and DCB<1:0>
Rollover/Reset
OCxR and DCB<1:0> Buffers
OC Clock
Sources
Trigger and
Sync Sources
Clock
Select
Increment
Reset
Trigger and ^{Match Event}
Sync Logic
Comparator
OCxTMR
Match
Event
Rollover
Comparator
OCxRS Buffer
Match
Event
Rollover/Reset
OCxRS
Reset
OCMx
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLTx
OCFLTx
DCB<1:0>
OCx Pin
OC Output Timing
and Fault Logic
OCFA/OCFB/CxOUT
OCx Interrupt
DS39995B-page 158
 2011 Microchip Technology Inc.