PIC24FV32KA304_1 Datasheet, PDF (168/320 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
R-0, HSC
R-0, HSC
SPIEN
—
SPISIDL
—
—
SPIBEC2
SPIBEC1
bit 15
R-0, HSC
SPIBEC0
bit 8
R-0,HSC
SRMPT
bit 7
R/C-0, HS R/W-0, HSC
SPIROV SRXMPT
R/W-0
SISEL2
R/W-0
SISEL1
R/W-0
SISEL0
R-0, HSC
SPITBF
R-0, HSC
SPIRBF
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6
bit 5
bit 4-2
SPIEN: SPI1 Enable bit
1 = Enables module and configures SCK1, SDO1, SDI1 and SS1 as serial port pins
0 = Disables module
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
Unimplemented: Read as ‘0’
SPIBEC<2:0>: SPI1 Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
SRMPT: Shift Register (SPI1SR) Empty bit (valid in Enhanced Buffer mode)
1 = SPI1 Shift register is empty and ready to send or receive
0 = SPI1 Shift register is not empty
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded
(The user software has not read the previous data in the SPI1BUF register.)
0 = No overflow has occurred
SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
SISEL<2:0>: SPI1 Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when last bit is shifted into SPI1SR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPI1SR; now the transmit is complete
100 = Interrupt when one data byte is shifted into the SPI1SR; as a result, the TX FIFO has one open spot
011 = Interrupt when SPIx receive buffer is full (SPIRBF bit set)
010 = Interrupt when SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT
bit is set)
DS39995B-page 168
 2011 Microchip Technology Inc.