PIC24FV32KA304_1 Datasheet, PDF (165/320 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
16.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the Serial
Peripheral Interface, refer to the “PIC24F
Family Reference Manual”, Section 23.
“Serial Peripheral Interface (SPI)”
(DS39699).
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial data EEPROMs, shift
registers, display drivers, A/D Converters, etc. The SPI
module is compatible with Motorola^® SPI and SIOP
interfaces.
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer.
Note:
Do not perform read-modify-write
operations (such as bit-oriented
instructions) on the SPI1BUF register in
either Standard or Enhanced Buffer mode.
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
The SPI serial interface consists of four pins:
• SDI1: Serial Data Input
• SDO1: Serial Data Output
• SCK1: Shift Clock Input or Output
• SS1: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module can be configured to operate using 2,
3 or 4 pins. In the 3-pin mode, SS1 is not used. In the
2-pin mode, both SDO1 and SS1 are not used.
Block diagrams of the module in Standard and
Enhanced Buffer modes are shown in Figure 16-1 and
Figure 16-2.
The devices of the PIC24FV32KA304 family offer two
SPI modules on a device.
Note:
In this section, the SPI modules are
referred to as SPIx. Special Function
Registers (SFRs) will follow a similar
notation. For example, SPI1CON1 or
SPI1CON2 refers to the control register
for the SPI1 module.
To set up the SPI1 module for the Standard Master
mode of operation:
1. If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0
register.
b) Set the respective SPI1IE bit in the IEC0
register.
c) Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
2. Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
3. Clear the SPIROV bit (SPI1STAT<6>).
4. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
5. Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
To set up the SPI module for the Standard Slave mode
of operation:
1. Clear the SPI1BUF register.
2. If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0
register.
b) Set the respective SPI1IE bit in the IEC0
register.
c) Write the respective SPI1IP bits in the IPC2
register to set the interrupt priority.
3. Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit
(SPI1CON1<7>) must be set to enable the SS1
pin.
6. Clear the SPIROV bit (SPI1STAT<6>).
7. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
 2011 Microchip Technology Inc.
DS39995B-page 165