PIC16LF1507 Datasheet, PDF (21/266 Pages) Microchip Technology – 20-Pin Flash, 8-Bit Microcontrollers

TABLE 3-3: PIC16(L)F1507 MEMORY MAP (CONTINUED)
400h
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
BANK 8
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
480h
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
BANK 9
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
—
NCO1ACCL
NCO1ACCH
NCO1ACCU
NCO1INCL
NCO1INCH
—
NCO1CON
NCO1CLK
500h
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
BANK 10
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
580h
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
BANK 11
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
600h
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
BANK 12
Core Registers
(Table 3-2)
—
—
—
—
—
PWM1DCL
PWM1DCH
PWM1CON
PWM2DCL
PWM2DCH
PWM2CON
PWM3DCL
PWM3DCH
PWM3CON
PWM4DCL
PWM4DCH
PWM4CON
—
—
—
680h
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
BANK 13
Core Registers
(Table 3-2)
—
—
—
—
—
CWG1DBR
CWG1DBF
CWG1CON0
CWG1CON1
CWG1CON2
—
—
—
—
—
—
—
—
—
—
700h
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
BANK 14
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
780h
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
BANK 15
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
46Fh
470h
47Fh
Common RAM
(Accesses
70h – 7Fh)
4EFh
4F0h
4FFh
Common RAM
(Accesses
70h – 7Fh)
56Fh
570h
57Fh
Common RAM
(Accesses
70h – 7Fh)
5EFh
5F0h
5FFh
Common RAM
(Accesses
70h – 7Fh)
64Fh
650h
67Fh
Common RAM
(Accesses
70h – 7Fh)
6EFh
6F0h
6FFh
Common RAM
(Accesses
70h – 7Fh)
76Fh
770h
77Fh
Common RAM
(Accesses
70h – 7Fh)
7EFh
7F0h
7FFh
Common RAM
(Accesses
70h – 7Fh)
BANK 16
BANK 17
BANK 18
800h
Core Registers
(Table 3-2)
880h
Core Registers
(Table 3-2)
900h
Core Registers
(Table 3-2)
80Bh
80Ch
Unimplemented
Read as ‘0’
88Bh
88Ch
Unimplemented
Read as ‘0’
90Bh
90Ch
Unimplemented
Read as ‘0’
86Fh
870h
87Fh
Common RAM
(Accesses
70h – 7Fh)
8EFh
8F0h
8FFh
Common RAM
(Accesses
70h – 7Fh)
96Fh
970h
97Fh
Common RAM
(Accesses
70h – 7Fh)
Legend:
= Unimplemented data memory locations, read as ‘0’
980h
98Bh
98Ch
9EFh
9F0h
9FFh
BANK 19
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A00h
A0Bh
A0Ch
A6Fh
A70h
A7Fh
BANK 20
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A80h
A8Bh
A8Ch
AEFh
AF0h
AFFh
BANK 21
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
B00h
B0Bh
B0Ch
B6Fh
B70h
B7Fh
BANK 22
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
B80h
B8Bh
B8Ch
BEFh
BF0h
BFFh
BANK 23
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)