PIC16LF1507 Datasheet, PDF (162/266 Pages) Microchip Technology – 20-Pin Flash, 8-Bit Microcontrollers

PIC16(L)F1507
20.1 CLCx Setup
Programming the CLCx module is performed by config-
uring the 4 stages in the logic signal flow. The 4 stages
are:
• Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
TABLE 20-1:
Data Input
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
CLCx DATA INPUT SELECTION
lcxd1
D1S
000
001
010
011
100
101
110
111
—
—
—
—
—
—
—
—
lcxd2
D2S
—
—
—
—
000
001
010
011
100
101
110
111
—
—
—
—
lcxd3
D3S
—
—
—
—
—
—
—
—
000
001
010
011
100
101
110
111
20.1.1 DATA SELECTION
There are 16 signals available as inputs to the configu-
rable logic. Four 8-input multiplexers are used to select
the inputs to pass on to the next stage. The 16 inputs to
the multiplexers are arranged in groups of four. Each
group is available to two of the four multiplexers, in
each case, paired with a different group. This arrange-
ment makes possible selection of up to two from a
group without precluding a selection from another
group.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers (Register 20-3 and Register 20-4,
respectively).
Data inputs are selected with CLCxSEL0 and
CLCxSEL1 registers (Register 20-3 and Register 20-4,
respectively).
Data selection is through four multiplexers as indicated
on the left side of Figure 20-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 20-1 correlates the generic input name to the
actual signal for each CLC module. The columns labeled
lcxd1 through lcxd4 indicate the MUX output for the
selected data input. D1S through D4S are abbreviations
for the MUX select input codes: LCxD1S<2:0> through
LCxD4S<2:0>, respectively. Selecting a data input in a
column excludes all other inputs in that column.
Note: Data selections are undefined at power-up.
lcxd4
D4S
100
101
110
111
—
—
—
—
—
—
—
—
000
001
010
011
CLC 1
CLC1IN0
CLC1IN1
Reserved
Reserved
FOSC
TMR0IF
TMR1IF
TMR2 = PR2
lcx1_out
lcx2_out
lcx3_out
lcx4_out
NCO1OUT
HFINTOSC
PWM3OUT
PWM4OUT
CLC 2
CLC2IN0
CLC2IN1
Reserved
Reserved
FOSC
TMR0IF
TMR1IF
TMR2 = PR2
lcx1_out
lcx2_out
lcx3_out
lcx4_out
LFINTOSC
ADCFRC
PWM1OUT
PWM2OUT
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 162