PIC24HJ32GP302_12 Datasheet, PDF (128/390 Pages) Microchip Technology – 16-bit Microcontrollers (up to 128 KB Flash and 8K SRAM) with Advanced Analog

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
9.4 Clock Switching Operation
Applications are free to switch among any of the four
clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, PIC24HJ32GP302/304,
PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04
devices have a safeguard lock built into the switch
process.
Note:
Primary Oscillator mode has three different
submodes (XT, HS and EC), which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
9.4.1 ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to Section 25.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
FSCM function are disabled. This is the default setting.
The NOSC<2:0> control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC<2:0> bits (OSC-
CON<14:12>) reflect the clock source selected by the
FNOSC<2:0> Configuration bits FOSCSEL<2:0>.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
9.4.2 OSCILLATOR SWITCHING SEQUENCE
Performing a clock switch requires this basic
sequence:
1. If required, read the COSC<2:0> bits to deter-
mine the current oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSC<2:0>
control bits for the new oscillator source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator
switch.
After the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC<2:0> status bits with the new value of the
NOSC<2:0> control bits. If they are the same,
the clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
2. If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and the CF
(OSCCON<3>) status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC<2:0>
status bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any pri-
mary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to Section 39. “Oscillator
(Part III)” (DS70308) in the “dsPIC33F/
PIC24H Family Reference Manual” for
details.
9.5 Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
If an oscillator fails, the FSCM generates a clock failure
trap event and switches the system clock over to the
FRC oscillator. Then the application program can either
attempt to restart the oscillator or execute a controlled
shutdown. The trap can be treated as a warm Reset by
simply loading the Reset address into the oscillator fail
trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
DS70293G-page 128
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