PIC24FJ64GA006-I Datasheet, PDF (103/258 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
8.4 Clock Switching Operation
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
Note:
Primary oscillator mode has three
different submodes (XT, HS and EC)
which are determined by the POSCMD
Configuration bits. While an application
can switch to and from primary oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
8.4.1 ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration bit
in the Flash Configuration Word 2 register must be pro-
grammed to ‘0’. (Refer to Section 24.1 “Configuration
Bits” for further details.) If the FCKSM1 Configuration bit
is unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is the
default setting.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is dis-
abled. However, the COSC bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled; it is held at ‘0’ at all
times.
8.4.2
OSCILLATOR SWITCHING
SEQUENCE
At a minimum, performing a clock switch requires this
basic sequence:
1. If desired, read the COSC bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator
switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, then the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
2. If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and CF (OSCCON<3>)
status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
4. The hardware waits for ten clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
6. The old clock source is turned off at this time
with the exception of LPRC (if WDT or FSCM is
enabled) or SOSC (if SOSCEN remains set).
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
2: Direct clock switches between any
primary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL
modes.
 2005-2012 Microchip Technology Inc.
DS39747F-page 103