MIC3002_10 Datasheet, PDF (60/65 Pages) Micrel Semiconductor – FOM Management IC with Internal Calibration

Micrel, Inc.
MIC3002
RX EEPOT Tap Selection (RXPOT)
D[7]
reserved
Default Value
Serial Address
D[6]
reserved
D[5]
reserved
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
A6h
D[2]
read/write
D[1]
read/write
D[0]
read/write
Byte Address
24 = 18h
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to these registers.
Bit(s)
D[7:5]
D[4:0]
Function
Reserved
RXPOT tap selection:
00000 = No divider action; POT
disconnected
00001 = 31/32
00010 = 30/32
•
•
•
11110 = 2/32
11111 = 1/32
Operation
Reserved. Always write as zero; reads undefined.
Read/write; non-volatile.
OEM Configuration 4 (OEMCFG4)
D[7]
reserved
Default Value
Serial Address
D[6]
reserved
D[5]
reserved
D[4]
D[3]
reserved
read/write
0000 0000b = 00h
A6h
D[2]
read/write
D[1]
read/write
D[0]
read/write
Byte Address
25 = 19h
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to these registers.
Bit(s)
D[7]
D[6]
D[5]
D[4]
Function
Allows Warnings to assert
TXFAULT
Allows Alarms to assert
TXFAULT
Warning Latch
Alarm Latch
Operation
0: Warnings do not assert TXFAULT
1: Warnings assert TXFAULT
The RXPWR low warning flag does not assert TXFAULT
0: Alarms do not assert TXFAULT
1: Alarms assert TXFAULT
The RXPWR low alarm flag does not assert TXFAULT
0: Warnings flags are latched. They are cleared by reading the register or
toggling TXDISABLE.
1: Warnings flags are not latched., i.e. they are set and reset with alarm
condition. The flags are also cleared by reading the register or toggling
TXDISABLE.
0: Alarms flags are latched. They are cleared by reading the register or
toggling TXDISABLE.
1: Alarms flags are not latched., i.e. they are set and reset with alarm
condition. The flags are also cleared by reading the register or toggling
TXDISABLE.
July 2007
60
M9999-073107-B
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