MLX75030 Datasheet, PDF (40/72 Pages) Melexis Microelectronic Systems – Universal ActiveLight Sensor Interface

MLX75030 Universal ActiveLight Sensor Interface
Datasheet
7.3. Internal Status Flags
Bit 7: Previous Command invalid/valid
When an uploaded command is considered invalid, bit 7 will be set high. This bit can be read out when the next command
will be uploaded. If the next command is valid, bit 7 will be cleared again.
A command is considered invalid in case:
- a command is unknown (i.e. all commands that are not mentioned in Table 13)
- the parity bit in the SM or SD command is not correct
- the parity bits in a WR command are not correct
- when a command (except the CR command) was sent during a measurement cycle (i.e. after uploading a SM/SD command,
when DR is still low)
- when a RO command was sent when DR is low (at any time, i.e. not only after uploading a SM/SD command)
- if a '1' is written into one of the bits of the 'Err' register
- if an ambient measurement is requested in case all bits EN_CH_C/EN_CH_D/EN_DIAGAMB are zero
Bit 6..5: Power State, Bit 4: Sleep request, Bit 3: Standby request
The behaviour of the power state and the sleep request bits is explained in Figure 15 : Power State and Sleep Request bits.
First a RSLP command is uploaded to the sensor. As a result of that, the sensor will put the status flag bit 4 (sleep request
flag) high. The master can read out that flag by uploading a NOP command, or when uploading other commands.
The master can confirm to go into sleep mode by uploading a CSLP command. The request flag will be reset and the sensor
will switch into sleep state. The status flag bits 6 and 5 will be set accordingly.
CS
SCLK
MOSI
MISO
Status Flag Bit 4
(Sleep Request)
Status Flag Bits 6..5
(Power State)
Device State
RSLP
(NOP)
CSLP
(NOP)
10
Normal Running Mode
00
Sleep State
NRM
10
Normal Running Mode
Figure 15 : Power State and Sleep Request bits
To go into standby mode, the same procedure shall be applied: uploading a RSTBY command makes the request standby flag
going high. Uploading a CSTBY will make the device going into standby mode, whereby the request standby flag will be
cleared and the power state bits will be set accordingly.
Bit 2: Device in TestMode/Normal Mode
To make the sensor efficiently testable in production, several test modes are foreseen to get easy access to different blocks.
The status flag bit 2 indicates if the device is operating in Test Mode or Normal Mode.
If the device enters test mode by accident, the application will still work like normal. However, the status flag bit 2 will be set
high. The master can take actions to get out of test mode by uploading a CR command.
Bit 1: Internal Oscillator is enabled/disabled
This bit is high when the internal oscillator is enabled. Once the RCO is shut down the bit will be set low.
Bit 0: Critical Error is detected/not detected
During each measurement cycle there is a monitoring of the voltage on critical nodes along the analog paths. When the
voltage of one of these controlled nodes goes out of its normal operating range, the Critical Error Flag will be set high.
REVISION 005 – DECEMBER 2013
3901075030
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