MLX75030 Datasheet, PDF (37/72 Pages) Melexis Microelectronic Systems – Universal ActiveLight Sensor Interface

MLX75030 Universal ActiveLight Sensor Interface
Datasheet
7.2.2.9. WR/RR – Write/Read Register
The slave contains several user registers that can be read and written by the master.
The WR and RR commands are used for that.
The WR command writes the contents of an 8-bit register addressed by bits A_3..0 with data D_7..0. Data is sent to the device
over the MOSI pin. Control2 Byte contains the 8 bit data that shall be written into the target register. Control3 Byte contains
the address of the target register.
The WR command is defined in the table below:
Control1 Byte
1000 0111
D₇D₆D₅D₄ D₃D₂D₁D₀
A₃A₂A₁A₀
P₁P₀
Data1 Byte
Status Flag Byte
Control2 Byte
D₇D₆D₅D₄ D₃D₂D₁D₀
Data contents of register to be written
Address of target register
Parity bits (P₁ = odd parity bit, P₀ = even parity bit)
Data2 Byte
1000 0111
Control3 Byte
A₃A₂A₁A₀ P₁P₀00
Data3 Byte
0000 0000
Table 17 : Write Register command
In order to detect some transmission errors while writing data towards the slave device, the micro-controller has to compute
an odd and an even parity bit of the Control2 and the 4 MSB's of the Control3 byte and send these parity bits to the slave.
The slave will check if the parity bits are valid. The data will only be written into the registers if the parity bits are correct. If
the parity bits are not correct, bit 7 of the internal Status Flag Byte will be set high, indicating that the command was invalid.
This can be seen when uploading a NOP command (when one is only interested in reading back the internal status flags) or
during upload of the next command.
In case the parity bits were not correct, the data of the registers will not be changed.
The parity bits calculation is based on the data D₇..D₀ and A₃..A₀. If the number of ones in the given data set [D₇..D₀, A₃..A₀] is
odd, the even parity bit P₀ shall be set to 1, making the total number of ones in the set [D₇..D₀, A₃..A₀, P₀] even.
Similar: if the number of ones in the given data set [D₇..D₀, A₃..A₀] is even, the odd parity bit P₁ shall be set to 1, making the
total number of ones in the set [D₇..D₀, A₃..A₀, P₁] odd.
Note that the parity bits can be generated with XOR instructions: P₁ = XNOR(D₇..D₀, A₃..A₀) and P₀ = XOR(D₇..D₀, A₃..A₀). The
odd parity bit P₁ should always be the inverse of the even parity bit P₀.
The RR command returns the contents of an 8-bit register addressed by bits A_3..0. Data is read back over the MISO pin. The
Data1 Byte contains the Internal Status Flag byte. Data2 Byte contains the copy of the Control1 Byte. Data3 Byte contains the
8 bits of the target register.
The RR command is defined in the table below:
REVISION 005 – DECEMBER 2013
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