MLX75030 Datasheet, PDF (26/72 Pages) Melexis Microelectronic Systems – Universal ActiveLight Sensor Interface

MLX75030 Universal ActiveLight Sensor Interface
Datasheet
LED driver will set the DAC voltage on external shunt resistor by a closed regulation loop.
7.1.7. POR
The Power On Reset (POR) is connected to voltage supply.
The POR cell generates a reset signal (high level) before the supply voltage exceeds a level from 2.7V.
The cell contains a hysteresis of 100mV.
Figure 7: POR sequence
7.2. SPI
7.2.1. General Description of SPI Interface
After power-on, the sensor enters a reset state (invoked by the internal power-on-reset circuit). A start-up time t_startup after
power-on, the internal reference voltages have become stable and a first measurement cycle can start. To indicate that the
start-up phase is complete, the DR pin will go high (DR is low during the start-up phase).
The control of this sensor is completely SPI driven. For each task to be executed, the proper command must be uploaded via
the SPI. The SPI uses a four-wire communication protocol. The following pins are used:
• CS: when CS pin is low, transmission and reception are enabled and the MISO pin is driven. When the CS pin goes high,
the MISO pin is no longer driven and becomes a floating output. This makes it possible that one micro-processor takes
control over multiple sensors by setting the CS pin of the appropriate sensor low while sending commands. The idle
state of the chip select is high.
• SCLK: clock input for the sensor. The clock input must be running only during the upload of a new command or during a
read-out cycle. The idle state of the clock input is high.
• MOSI: data input for uploading the different commands and the data that needs to be written into some registers. The
idle state of the data input is low.
• MISO: data output of the sensor.
A SPI timing diagram is given in Figure 8. This is the general format for sending a command. First the CS pin must be set low
so that the sensor can accept data. The low level on the CS pin in combination with the first rising clock edge is used to start
an internal synchronization counter that counts the incoming bits. Data on the MOSI pin is clocked in at the rising clock edge.
Data on the MISO pin is shifted out during the falling clock edge. Note that the tri-state of the MISO pin is controlled by the
state of CS.
After uploading a command, the CS pin must be set high for a minimum time of t_{cs_inter} in order to reset the internal
synchronization counter and to allow new commands to be interpreted.
REVISION 005 – DECEMBER 2013
3901075030
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