MCF5407AI162 Datasheet, PDF (90/546 Pages) Micro Commercial Components – Integrated Microprocessor Users Manual

Execution Timings
In this sequence, the second instruction is held for three cycles stalling for the
multiply instruction to update d0. If consecutive instructions update a register and
use that register as a base of index value with a scale factor of 1 (Xi.l*1) in an address
calculation, a two-cycle pipeline stall occurs. Using the destination register as an
index register with any other scale factor (Xi.l*2, Xi.l*4) causes a three-cycle stall.
Some instructions are optimized to ensure against causing such stalls on subsequent
instructions. The destination register on the following instructions is always
available for subsequent instructions:
lea
<ea>y,Ax
move.l #<data>,Rx
mov.w #<data>,Ax
moveq #<data>,Dx
clr.l Dx
mov3q.l #<data>,Rx
<op> (Ay)+,Rx
<op> -(Ay),Rx
<op> Ry,(Ax)+
<op> Ry,-(Ax)
Note that the address register results from postincrement and predecrement modes
are available to subsequent instructions without stalls.
• The OEP can complete all memory accesses without memory causing any stall
conditions. Thus, timing details in this section assume an infinite zero-wait state
memory attached to the core.
• Operand data accesses are assumed to be aligned on the same byte boundary as the
operand size:
— 16-bit operands aligned on 0-modulo-2 addresses
— 32-bit operands aligned on 0-modulo-4 addresses
Operands not meeting these guidelines are misaligned. Table 2-10 shows how the
core decomposes a misaligned operand reference into a series of aligned accesses.
Table 2-10. Misaligned Operand References
A[1:0]
Size
Bus Operations
Additional C(R/W) ¹
Read
Write
x1
Word
Byte, Byte
2(1/0)
1(0/1)
x1
Long
Byte, Word, Byte
3(2/0)
2(0/2)
10
Long
Word, Word
2(1/0)
1(0/1)
1 _{Each timing entry is presented as C(R/W), described as follows:}
C is the number of processor clock cycles, including all applicable operand fetches and writes, as well as all
internal core cycles required to complete the instruction execution.
R/W is the number of operand reads (r) and writes (w) required by the instruction. An operation performing a
read-modify write function is denoted as (1/1).
2-24
MCF5407 User’s Manual