MCF5407AI162 Datasheet, PDF (419/546 Pages) Micro Commercial Components – Integrated Microprocessor Users Manual

Clock and Reset Signals
17.4.3 Bus Driven (BD)
The MCF5407 asserts BD to indicate that it is the current master and is driving the bus. The
MCF5407 behaves as follows:
• If the MCF5407 is the bus master but is not using the bus, BD is asserted.
• If the MCF5407 loses mastership during a transfer, it completes the last transfer of
the access, negates BD, and three-states all bus signals on the rising edge of CLKIN.
• If the MCF5407 loses bus mastership during an idle clock cycle, it three-states all
bus signals on the rising edge of CLKIN.
• BD cannot be negated unless BG is negated.
17.5 Clock and Reset Signals
The clock and reset signals configure the MCF5407 and provide interface signals to the
external system.
17.5.1 Reset In (RSTI)
Asserting RSTI causes the MCF5407 to enter reset exception processing. When RSTI is
recognized, BR and BD are negated and the address bus, data bus, TT, SIZ, R/W, AS, and
TS are three-stated. RSTO is asserted automatically when RSTI is asserted.
17.5.2 Clock Input (CLKIN)
CLKIN is the MCF5407 input clock frequency to the on-board phase-locked-loop (PLL)
clock generator. CLKIN is used to internally clock or sequence the MCF5407 internal bus
interface at a selected multiple of the input frequency used for internal module logic.
CLKIN should be used as the bus timing reference.
17.5.3 Bus Clock Output (BCLKO)
The internal PLL generates BCLKO. It has the same frequency as CLKIN, which is used
as the bus timing reference by the external devices. BCLKO is provided for compatibility
with earlier devices.
17.5.4 Reset Out (RSTO)
After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is
asserted. When the PLL regains its lock, RSTO negates again. This signal can be used to
reset external devices.
Chapter 17. Signal Descriptions
17-13