MCF5407AI162 Datasheet, PDF (180/546 Pages) Micro Commercial Components – Integrated Microprocessor Users Manual

Background Debug Mode (BDM)
• A B marker occurs on the right nibble of PSTDDATA with the data of 0xFF
following:
PSTDDATA[7:0]
0xYB
0xFF
0xFF
0xFF
0xFF
0xXY (X indicates that the PST value is guaranteed to not be 0xF; and Y indicates
a PSTDDATA value that doesn’t affect the 0xFF count).
Thus, a count of either nine or more sequential single 0xF values or five or more sequential
0xFF values signifies the HALT condition.
5.5.2 BDM Serial Interface
When the CPU is halted and PSTDDATA reflects the halt status, the development system
can send unrestricted commands to the debug module. The debug module implements a
synchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), where
DSCLK and DSI must meet the required input setup and hold timings and the DSO is
specified as a delay relative to the rising edge of the processor clock. See Table 5-1. The
development system serves as the serial communication channel master and must generate
DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the processor frequency. The
channel uses full-duplex mode, where data is sent and received simultaneously by both
master and slave devices. The transmission consists of 17-bit packets composed of a
status/control bit and a 16-bit data word. As shown in Figure 5-15, all state transitions are
enabled on a rising edge of the processor clock when DSCLK is high; that is, DSI is
sampled and DSO is driven.
CPU CLK
C1
C2
C3
C4
PSTCLK
DSCLK
DSI
BDM State
Machine
DSO
Current
Next
Current State
Next State
Past
Current
Figure 5-15. BDM Serial Interface Timing
5-24
MCF5407 User’s Manual