MCF5407AI162 Datasheet, PDF (518/546 Pages) Micro Commercial Components – Integrated Microprocessor Users Manual

Revision C Debug
Vector
12
13
Table A-12. Debug C Exception Vector Assignments
Vector Offset
0x030
0x034
Stacked Program Counter
Next
Next
Assignment
Non-PC-breakpoint debug interrupt
PC-breakpoint debug Interrupt
A.8.5 Processor Status and Debug Data Output Signals
The Debug B architecture defines processor status, PST[3:0] and debug data DDATA[3:0]
signals, which provide information to support real-time trace. In the Debug B design, these
signals are output at the processor frequency.
For the Debug C definition, however, the PST and DDATA are combined and redefined to
operate at half the processor’s operating frequency (provided by PSTCLK). Therefore,
PSTDDATA[7:0] are used to output both processor status and captured debug data values.
For more details, including single-cycle instruction timing examples, see Section 5.2.1,
“Processor Status/Debug Data (PSTDDATA[7:0]).”
A PST marker and its data display are transmitted contiguously. Except for this
transmission, the IDLE status (0x0) may appear any time. Again, given the real-time trace
information appears as a sequence of 4-bit values, there are no alignment restrictions. That
is, PST values and operands may appear on either nibble of PSTDDATA.
In Debug B, the DDATA outputs display the status of the internal breakpoint registers when
they are not displaying captured data values. For the Debug C design, any change to this
breakpoint state is identified by a PST marker and then the new state value. Specifically, the
marker for this breakpoint state change is a single assertion of the value 0xD. Usually, the
0xD status is asserted for multiple cycles, indicating entry into emulator mode in response
to a debug interrupt exception. For Debug C, the posting of the 0xD status can signal
multiple events, based on the next value.
if the PSTDDATA stream includes {0xD, 0x2}
then Breakpoint state changed to Waiting for Level 1 Trigger
if the PSTDDATA stream includes {0xD, 0x4}
then Breakpoint state changed to Level 1 Breakpoint Triggered
if the PSTDDATA stream includes {0xD, 0xA}
then Breakpoint state changed to Waiting for Level 2 Trigger
if the PSTDDATA stream includes {0xD, 0xC}
then Breakpoint state changed to Level 2 Breakpoint Triggered
if the PSTDDATA stream includes {0xD, 0xD}
then Entry into Emulator Mode
Table A-13 shows the revised definition of the processor status encodings, where the values
of {0xC–0xF} are usually asserted for multiple cycles. The behavior of the 0xD value was
described previously. The PSTDDATA values of 0x2 and 0x6 are formerly reserved values
now needed to support the Version 4 operand execution pipeline.
A-16
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