MCF5407AI162 Datasheet, PDF (279/546 Pages) Micro Commercial Components – Integrated Microprocessor Users Manual

Asynchronous Operation
Table 11-9. DRAM Addressing for 32-Bit Wide Memories
MCF5407 Address
Pin
15
14
13
12
11
10
9
17
19
21
23
25
MCF5407 Address Bit
Driven for RAS
15
14
13
12
11
10
9
17
19
21
23
25
MCF5407 Address Bit Driven
when CAS is Asserted
2
3
4
5
6
7
8
16
18
20
22
24
Memory Size
Base Memory Size of
64 Kbytes
256 Kbytes
1 Mbyte
4 Mbytes
16 Mbytes
64 Mbytes
11.3.3.1 Non-Page-Mode Operation
In non-page mode, the simplest mode, the DRAM controller provides termination and runs
a separate bus cycle for each data transfer. Figure 11-5 shows a non-page-mode access in
which a DRAM read is followed by a write. Addresses for a new bus cycle are driven at the
rising clock edge.
For a DRAM block hit, the associated RAS is driven at the next falling edge. Here
DACRn[RCD] = 0, so the address is multiplexed at the next rising edge to provide the
column address. The required CAS signals are then driven at the next falling edge and
remain asserted for the period programmed in DACRn[CAS]. Here, DACRn[RNCN] = 1,
so it is precharged one clock before CAS is negated. On a read, data is sampled on the last
rising edge of the clock that CAS is valid.
CLKIN
A[31:0]
Row
Column
RAS[1] or [0]
CAS[3:0]
DRAMW
DACRn[RCD] = 0 DACRn[RNCN] = 1
DACRn[CAS] = 01]
D[31:0]
Figure 11-5. Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4)
Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-11