MCF5407AI162 Datasheet, PDF (514/546 Pages) Micro Commercial Components – Integrated Microprocessor Users Manual

Revision C Debug
A.8.2 On-Chip Breakpoint Registers
The Debug B core debug module included three basic types of on-chip breakpoint registers:
• A 32-bit PC breakpoint register and a 32-bit PC breakpoint mask
• Two 32-bit address registers, which can be used to specify a single address or a range
of addresses
• A 32-bit data breakpoint register and a 32-bit data breakpoint mask
The mask registers can be used to “don’t care” the equivalent bits in the breakpoint
registers.
Additions to the breakpoint implementation are as follows:
• Three more 32-bit PC breakpoint registers
• Two more 32-bit address registers (ABLR1, ABHR1) plus an attribute register
(AATR1) and mask register, which can be used to specify a single address or a range
of addresses
• One more 32-bit data breakpoint register and a 32-bit data breakpoint mask
The addition of these new breakpoint registers also requires the appropriate control and
configuration functions be added to the debug programming model. The affected BDM
command and new register formats are described below. The revised BDM command is
write debug module register (WDMREG).
A.8.2.1 Write Debug Module Register (WDMREG)
The operand (longword) data is written to the specified debug module register. All 32 bits
of the register are altered by the write operation. The debug module’s programming model
can be accessed either from the serial BDM communication channel or from the processor’s
execution of the supervisor-mode WDEBUG instruction. DSCLK must be inactive while
WDEBUG executes.
Figure A-5 defines the operand data format.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x2
0xC
0x4
DRc
D[31:16]
D[15:0]
Figure A-5. Write Debug Module Register Command (WDMREG)
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MCF5407 User’s Manual