MCF5407AI162 Datasheet, PDF (483/546 Pages) Micro Commercial Components – Integrated Microprocessor Users Manual

Input/Output AC Timing Specifications
Table 20-7. Output AC Timing Specification (Continued)
Num
Characteristic
B13 ^8,2,3
B14 ^8,2,3
B15 ^2,3
B16 ^2,3
CLKIN rising to valid
CLKIN rising to invalid (hold)
EDGESEL to valid
EDGESEL to invalid (hold)
54 MHz CLKIN
Min
Max
—
0.5(C1) +8.0 ⁹
—
0.5(C1) +10.0 ¹⁰
0.5(C1) + 1.0
—
—
12
2
—
Units
nS
nS
nS
nS
nS
H1
HIZ to high impedance
—
60
nS
H2
HIZ to low Impedance
—
60
nS
1 _{Outputs that change only on rising edge of CLKIN: RSTO, TS, BR, BD, TA, R/W, SIZ[1:0], PP[7:0]}
(and PP[15:8] when configured as parallel port outputs).
2 _{Outputs that can change on either CLKIN edge depending only on EDGESEL: D[31:0], A[23:0],}
SCKE, SRAS, SCAS, and DRAMW and on PP[15:8] when individually configured as A[31:24]
outputs.
3 _{Outputs that can change on either CLKIN edge depending upon EDGESEL and the interface}
operating mode (DRAM/SDRAM): RAS[1:0], CAS[3:0]
4 _{SRAS, SCAS, DRAMW, RAS[1:0], CAS[3:0]}
5 _{D[31:0], A[23:0], TM[2:0], TT[1:0], SIZ[1:0], R/W, TIP, TS, BR, BD, and TA and PP[15:8] when}
individually configured as A[31:24] outputs.
6 _{High impedance (three-state): D[31:0]}
7 _{Outputs that transition to high impedance due to bus arbitration: A[23:0], R/W, SIZ[1:0], TS, AS,}
and TA, and PP[15:8] when individually configured as A[31:24] outputs.
8 _{Outputs that change only on falling edge of CLKIN: AS, CS[7:0], BE[3:0], OE}
9 _{SRAS, SCAS, DRAMW, RAS[1:0], CAS[3:0], AS, CS[7:0], BE[3:0], OE}
10 _{D[31:0], A[23:0], TM[2:0], TT[1:0], SIZ[1:0], R/W, TIP, and TS and on PP[15:8] when individually}
configured as A[31:24] outputs.
Note that these figures show two representative bus operations and do not attempt to show
all cases. For explanations of the states, S0–S5, see Section 18.4, “Data Transfer
Operation.” Note that Figure 20-7 does not show all signals that apply to each timing
specification. See the previous tables for a complete listing.
Figure 20-6 shows AC timings for normal read and write bus cycles.
Chapter 20. Electrical Specifications
20-7