MAX1265 Datasheet, PDF (9/19 Pages) Maxim Integrated Products – 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
the analog inputs. This configuration is pseudo-differ-
ential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C_HOLD. At the
end of the acquisition interval, the T/H switch opens,
retaining charge on C_HOLD as a sample of the signal
at IN+.
The conversion interval begins with the input multiplex-
er switching C_HOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder
12-BIT CAPACITIVE DAC
V_REF
CH0
INPUT
MUX
C_HOLD
–+
ZERO
12pF
CH1
R_IN
CH2
C_SWITCH
800Ω
CH3
TRACK
HOLD
CH4
CH5
T/H
SWITCH
COM
COMPARATOR
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1, CH2/CH3, AND CH4/CH5
Figure 3a. MAX1265 Simplified Input Structure
12-BIT CAPACITIVE DAC
V_REF
CH0
INPUT
MUX
C_HOLD
–+
ZERO
12pF
CH1
R_IN
C_SWITCH
800Ω
HOLD
TRACK
T/H
SWITCH
COM
COMPARATOR
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1
Figure 3b. MAX1267 Simplified Input Structure
Table 1. Control-Byte Functional Description
BIT
NAME
FUNCTIONAL DESCRIPTION
D7, D6
D5
D4
D3
D2, D1, D0
PD1 and PD0 select the various clock and power-down modes.
0
0
Full power-down mode. Clock mode is unaffected.
PD1, PD0
0
1
Standby power-down mode. Clock mode is unaffected.
1
0
Normal operation mode. Internal clock mode selected.
1
1
Normal operation mode. External clock mode selected.
ACQMOD
SGL/DIF
UNI/BIP
A2, A1, A0
ACQMOD = 0: Internal acquisition mode
ACQMOD = 1: External acquisition mode
SGL/DIF = 0: Pseudo-differential analog input mode
SGL/DIF = 1: Single-ended analog input mode
In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference
between two channels is measured (Tables 2 and 4).
UNI/BIP = 0: Bipolar mode
UNI/BIP = 1: Unipolar mode
In unipolar mode, an analog input signal from 0V to V_REF can be converted; in bipolar mode, the
signal can range from -V_REF/2 to +V_REF/2.
Address bits A2, A1, A0 select which of the 6/2 (MAX1265/MAX1267) channels are to be converted
(Tables 2 and 3).
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