MAX1265 Datasheet, PDF (10/19 Pages) Maxim Integrated Products – 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2
A1
A0
CH0
0
0
0
+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
*Channels CH2–CH5 apply to MAX1265 only.
CH1
+
CH2*
+
CH3*
+
CH4*
CH5*
+
+
COM
-
-
-
-
-
-
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A2
A1
A0
CH0
CH1
CH2*
CH3*
CH4*
0
0
0
+
-
0
0
1
-
+
0
1
0
+
-
0
1
1
-
+
1
0
0
+
1
0
1
-
*Channels CH2–CH5 apply to MAX1265 only.
CH5*
-
+
of the conversion cycle to restore node 0 to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF (V_IN+ - V_IN-) charge from C_HOLD to
the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V_DD and GND, allow each input channel to
swing within (GND - 300mV) to (V_DD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (V_DD + 50mV) or be
less than (GND - 50mV).
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
Track/Hold
The MAX1265/MAX1267 T/H stage enters its tracking
mode on WR’s rising edge. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this is approximately 1µs after writing the control
byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive (+) input. In
pseudo-differential operation, IN- connects to the nega-
tive (-) input, and the difference of _|(IN+) - (IN-)_| is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
t_ACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
t_ACQ = 9(R_S + R_IN)C_IN
where R_S is the source impedance of the input signal,
R_IN (800Ω) is the input resistance, and C_IN (12pF) is
the input capacitance of the ADC. Source impedances
below 3kΩ have no significant impact on the MAX1265/
MAX1267s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
10 ______________________________________________________________________________________