MAX1265 Datasheet, PDF (16/19 Pages) Maxim Integrated Products – 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
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CLK
;^WR
RD
CONTROL
D11–
D7–D0 _WORD
D0
STATE
ACQUISITION
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
CONTROL WORD
CONVERSION
;D11–D0
ACQUISITION
SUPPLIES
+3V
+3V GND
*R = 5Ω
4.7µF
0.1µF
V_DD
GND
COM
*OPTIONAL
MAX1265
MAX1267
+3V DGND
DIGITAL
CIRCUITRY
Figure 11. Power-Supply and Grounding Connections
acquisition cycle of the next conversion, then reading the
results of the previous conversion from the bus. This
technique (Figure 10) allows a conversion to be com-
pleted every 16 clock cycles. Note that the switching of
the data bus during acquisition or conversion can
cause additional supply noise, which can make it diffi-
cult to achieve true 12-bit performance.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 11) connecting the two ground
systems (analog and digital). For lowest noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply, V_DD, could
impair operation of the ADC’s fast comparator. Bypass
V_DD to the star ground with a network of two parallel
capacitors, 0.1µF and 4.7µF, located as close as to the
MAX1265/MAX1267s’ power-supply pin as possible.
Minimize capacitor lead length for best supply-noise
rejection and add an attenuation resistor (5Ω) if the
power supply is extremely noisy.
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