MAX1265 Datasheet, PDF (14/19 Pages) Maxim Integrated Products – 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 4. Control-Byte Format
D7
(MSB)
D6
D5
D4
D3
D2
PD1
PD0
ACQMOD
SGL/DIF
UNI/BIP
A2
D1
D0
(LSB)
A1
A0
V_DD = +3V
50kΩ
50kΩ
330kΩ
GND
0.01µF
4.7µF
MAX1265
MAX1267
REFADJ
REF
GND
Figure 7. Reference Adjustment with External Potentiometer
select signal, which enables a µP to address the
MAX1265/MAX1267 as an I/O port. When high, CS dis-
ables the CLK, WR, and RD inputs and forces the inter-
face into a high-impedance (high-Z) state.
Input Format
The control bit sequence is latched into the device on
pins D7–D0 during a write command. Table 4 shows
the control-byte format.
Output Data Format
The 12-bit-wide output format for both the MAX1265/
MAX1267 is binary in unipolar mode and two’s comple-
ment in bipolar mode. CS, RD, WR, INT, and the 12 bits
of output data can interface directly to a 16-bit data bus.
When reading the output data, CS and RD must be low.
__________Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1265/MAX1267 in external clock
mode and sets INT high. After the power supplies stabi-
lize, the internal reset time is 10µs; no conversions
should be attempted during this phase. When using the
internal reference, 500µs is required for V_REF to stabilize.
Internal and External Reference
The MAX1265/MAX1267 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
An internal buffer is designed to provide +2.5V at REF for
both the MAX1265 and MAX1267. The internally trimmed
+1.22V reference is buffered with a +2.05V/V gain.
Internal Reference
The full-scale range with the internal reference is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize noise on the
reference, connect a 0.01µF capacitor between REFADJ
and GND.
External Reference
With both the MAX1265 and MAX1267, an external refer-
ence can be placed at either the input (REFADJ) or the
output (REF) of the internal reference buffer amplifier.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17kΩ.
When applying an external reference to REF, disable
the internal reference buffer by connecting REFADJ to
V_DD. The DC input resistance at REF is 25kΩ.
Therefore, an external reference at REF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10Ω. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.
Power-Down Modes
To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 4). In both software power-
down modes, the parallel interface remains active, but
the ADC does not convert.
Standby Mode
While in standby mode, the supply current is typically
850µA. The part powers up on the next rising edge of
WR and is ready to perform conversions. This quick
turn-on time allows the user to realize significantly
reduced power consumption for conversion rates
below 265ksps.
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