MAX1265 Datasheet, PDF (7/19 Pages) Maxim Integrated Products – 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
PIN
MAX1265 MAX1267
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
—
17
—
18
—
19
—
20
16
21
17
22
18
23
19
24
20
NAME
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
INT
RD
WR
CLK
CS
CH5
CH4
CH3
CH2
CH1
CH0
COM
GND
REFADJ
Pin Description
FUNCTION
Tri-State Digital Output (D9)
Tri-State Digital Output (D8)
Tri-State Digital I/O Line (D7)
Tri-State Digital I/O Line (D6)
Tri-State Digital I/O Line (D5)
Tri-State Digital I/O Line (D4)
Tri-State Digital I/O Line (D3)
Tri-State Digital I/O Line (D2)
Tri-State Digital I/O Line (D1)
Tri-State Digital I/O Line (D0)
INT goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read opera-
tion on the data bus.
Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conver-
sion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock.
In internal clock mode, connect this pin to either V_DD or GND.
Active-Low Chip Select. When CS is high, digital outputs (D11–D0) are high
impedance.
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5 LSB during conversion.
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01µF capacitor. When using an external reference, connect REFADJ to V_DD to
disable the internal bandgap reference.
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