MAX1265 Datasheet, PDF (4/19 Pages) Maxim Integrated Products – 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS
(V_DD = +2.7V to +3.6V, COM = GND, REFADJ = V_DD, V_REF = +2.5V, 4.7µF capacitor at REF pin, f_CLK = 4.8MHz (50% duty cycle),
T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
Data Valid to WR Rise Time
WR Rise to Data Valid Hold Time
WR to CLK Fall Setup Time
CLK Fall to WR Hold Time
CS to CLK or WR Setup Time
CLK or WR to CS Hold Time
CS Pulse Width
WR Pulse Width
CS Rise to Output Disable
RD Rise to Output Disable
RD Fall to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
SYMBOL
t_CP
t_CH
t_CL
t_DS
t_DH
t_CWS
t_CWH
t_CSWS
t_CSWH
t_CS
t_WR
t_TC
t_TR
t_DO
t_INT1
t_DO2
CONDITIONS
(Note 8)
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
MIN TYP MAX UNITS
208
ns
40
ns
40
ns
40
ns
0
ns
40
ns
40
ns
60
ns
0
ns
100
ns
60
ns
20
100
ns
20
70
ns
20
70
ns
100
ns
110
ns
Note 1: Tested at V_DD = +3V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V_DD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
DOUT
6kΩ
C_LOAD
20pF
V_DD
3kΩ
DOUT
C_LOAD
20pF
a) HIGH-Z TO V_OH AND V_OL TO V_OH
b) HIGH-Z TO V_OL AND V_OH TO V_OL
Figure 1. Load Circuits for Enable/Disable Times
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