MAX1265 Datasheet, PDF (8/19 Pages) Maxim Integrated Products – 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
PIN
MAX1265 MAX1267
25
21
26
22
27
23
28
24
NAME
REF
V_DD
D11
D10
Pin Description (continued)
FUNCTION
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor
to GND when using the internal reference.
Analog +2.7V to +3.6V Power Supply. Bypass with a 0.1µF capacitor to GND.
Tri-State Digital Output (D11)
Tri-State Digital Output (D10)
(CH5)
(CH4)
(CH3)
(CH2)
CH1
CH0
COM
CLK
ANALOG
INPUT
MULTIPLEXER
CLOCK
REF
REFADJ
17kΩ
A_V =
1.22V
2.05
REFERENCE
T/H
CHARGE REDISTRIBUTION
12-BIT DAC
12
SUCCESSIVE-
APPROXIMATION
REGISTER
COMP
CS
WR
CONTROL LOGIC
AND
RD
LATCHES
INT
MAX1265
MAX1267
12
V_DD
TRI-STATE, BIDIRECTIONAL
GND
I/O INTERFACE
D0–D11
12-BIT DATA BUS
( ) ARE FOR MAX1265 ONLY.
Figure 2. Simplified Functional Diagram of 6-/2-Channel MAX1265/MAX1267
________________Detailed Description
Converter Operation
The MAX1265/MAX1267 ADCs use a successive-
approximation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal
to a 12-bit digital output. This output format provides an
easy interface to standard microprocessors (µPs). Figure
2 shows the simplified internal architecture of the
MAX1265/MAX1267.
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1265
(Figure 3a) and to CH0–CH1 for the MAX1267 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
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