MAX1101 Datasheet, PDF(8/12 Page) Maxim Integrated Products – Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA

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MAX1101 Datasheet, PDF (8/12 Pages) Maxim Integrated Products – Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA

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Single-Chip, 8-Bit CCD Digitizer

with Clamp and 6-Bit PGA

MODE

SCLK

LOAD

DATA

tMSU

tSPW

tSL

tLS

tLD

tDSU

tDH

Figure 7. MODE = 0 Timing

CCD OUT

VIDSAMP

CLAMP

SCLK

DATA

RESET FEEDTHROUGH

tVR

tCPW

tVLS

tRB

tVB

tVLD

tSD

Figure 8. MODE = 1 Timing

PRECHARGE LEVEL

tVS

tBS

tBC

tVB

VIDEO LEVEL

DATA OUTPUT AFTER D0 IS UNSPECIFIED

LOAD controls the loading of data into the internal stor-

age registers during data input. Once all eight input bits

have been clocked into the shift register, a rising edge on

LOAD clocks the data into the appropriate storage regis-

ter (mux or PGA), decoded from the first two input bits.

The logic is divided into four blocks: the two storage reg-

isters, the serial I/O port, and a power-on reset genera-

tor. The registers are reset by the power-on reset to

place them in a predictable state (input channel = CCD,

PGA gain = -2) on power-up. The power-on reset typical-

ly has a 2.1Âµs pulse width.

The serial I/O port consists of a shift register, an 8-bit

storage register, decode logic to clock input data into

the appropriate storage register, and an output driver.

The 8-bit storage register takes input data from the

ADC.

Input Buffers and Output Drivers

The DATA driver is capable of driving 50pF load capaci-

tance while meeting the output delay specifications

given in the Electrical Characteristics. The gates of the P-

channel and N-channel drivers are driven separately. If

MODE is low, both drivers are off and the output is high

impedance.

The VIDSAMP, CLAMP, SCLK, and LOAD inputs are

buffered and have hysteresis to reject noise with slow-

slewing signal edges.

__________Applications Information

MAX1101 Timing

Figure 7 shows the timing configuration when MODE =

0 and data is loaded into the MAX1101. Figure 8 shows

timing when MODE = 1 and the CCD signal is digitized.

Figure 9 is an expansion of Figure 8, illustrating the

two-VIDSAMP-cycle data latency. Figure 10 shows the

relationship of CLAMP to VIDSAMP when MODE = 1.

8 _______________________________________________________________________________________

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