MAX1101 Datasheet, PDF (5/12 Pages) Maxim Integrated Products – Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA

Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
REF+
CLAMP
FROM
S2
CCD
C_EXT
0.047µF
REF+
S1
C_I
REF-
S1
CF
S2
S1P
TO
ADC
REF-
VIDSAMP
S1*
S2*
S1P*
ON
OFF
OFF
ON
OFF
ON
* INTERNALLY GENERATED SIGNALS
Figure 2. PGA Functional Diagram
Programmable-Gain Amplifier
The PGA amplifies the differential video signal from the
CCD (at CCDIN). Gain is settable with the 6-bit con-
trol word from -2 to -10 in 64 steps, in increments of
-0.125. The PGA also provides for periodic DC restora-
tion of the capacitively coupled input.
As shown in Figure 2, the switched-capacitor amplifier’s
gain is set by the ratio C_I/C_F. The input is sampled on
the C_I capacitors, which is a set of equal capacitors.
The 6-bit gain control word determines the number
of capacitors used. Thus the PGA gain is set from
-2 to -10.
A voltage equal to V_REF- is applied to the PGA’s nonin-
verting input. This offsets the PGA output to be within
the range of the ADC (V_REF- to V_REF+).
Clamp Circuit
As shown in Figure 2, the CCD output is connected to
the MAX1101 input (CCDIN) through an external
capacitor, which removes the potentially large DC
common-mode voltages from the input signal.
Whenever CLAMP is high, the CLAMP switch is closed
and C_EXT is charged to V_REF+. It can be actuated
either once per pixel (sampling reset level) or less fre-
quently (such as for restoring optical black level once
per line), as required by the application.
REF+ _REF-
C_F
C_I
V_OUT = V_REF- ±V_0S
REF-
Figure 3a. PGA Connection with VIDSAMP = Low
C_F
V_REF+
C_I
- V_VIDEO
(FROM DC
RESTORE)
REF-
Figure 3b. PGA Connection with VIDSAMP = High
VIDSAMP controls the sampling of the video signal
and offset nulling of the PGA. To null out the offset,
VIDSAMP causes switches S1 and S1P to close, plac-
ing the amplifier in a unity-gain configuration, as shown
in Figure 3a. This configuration causes the amplifier’s
offset voltage to be stored on CF. In the next portion of
the cycle, when VIDSAMP returns low, the S1 switches
are opened and S2 is closed (Figure 3b). This is the
standard inverting op-amp configuration. The only dif-
ference is that capacitors are used to set the gain, and
the amplifier’s offset voltage has been stored on these
capacitors and is thus canceled. The amplifier’s output
is [C_F/C_I] x V_VIDEO + V_REF-. The CDS function is shown
in Figure 4.
ADC
The ADC uses a recycling half-flash conversion tech-
nique in which a 4-bit flash ADC section achieves an
8-bit result in two steps (Figure 5). Using 15 compara-
tors, the flash ADC compares the unknown input
voltage to the reference ladder (using REF+ and REF-)
and provides the upper four data bits.
An internal digital-to-analog converter (DAC) uses the
four most significant bits (MSBs) to generate the analog
result from the first flash conversion and a residue volt-
age that is the difference between the unknown voltage
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