MAX1101 Datasheet, PDF (6/12 Pages) Maxim Integrated Products – Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA

Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
CCD OUTPUT
CLAMP PULSE
(CLAMP)
CLAMP OUTPUT
V_VIDEO
CCD OUTPUT
LEVELS VARY
DUE TO CCD
RESET NOISE
VOLTAGE OF
RESET SECTION
IS SET TO V_REF+
BY CLAMP
SAMPLE-AND-HOLD PULSE
(VIDSAMP)
Figure 4. Correlated Double Sampler (CDS)
and the DAC output. The residue is then compared
again with the flash comparators to obtain the lower
four data bits.
Single-shot timers control the timing of the two conver-
sion steps. Once both MSBs and LSBs have been
determined, the comparators return to input-acquisi-
tion/auto-zero mode.
REF+ and REF-
The REF+ and REF- pins set the ADC’s full-scale range.
The optimum input range is +0.5V to +3.0V. Figure 6
shows a matched resistive ladder that generates the
reference voltages. Four pins are available: REF+,
REF-, REFBIAS, and REFGND. If 5.00V is applied to
REFBIAS while REFGND is grounded, then 3.00V and
0.50V are generated at REF+ and REF-, respectively.
For increased accuracy or power-supply immunity,
REF+ can be connected to an external +3.00V refer-
ence. If this is done, the accuracy must be better than
±5%. REFBIAS should be left open in this case.
Multiplexer
The mux selects either the output of the PGA or one of
two other inputs to the ADC. The mux switching is
break-before-make to prevent transient shorts between
channels. The first two bits of the input control byte
select the mux input channel (Table 1).
REF+
REF-
FROM
MUX
4-BIT
FLASH
ADC
4-BIT
DAC
VREF+
16
4-BIT
FLASH
ADC
(4LSB)
OUTPUT
REGISTER
DATA
OUT
Figure 5. ADC Functional Diagram
Serial-Interface Logic
The serial interface inputs and outputs data in 8-bit
words. The interface is controlled by four signals:
MODE, LOAD, DATA, and SCLK.
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