MAX1101 Datasheet, PDF (4/12 Pages) Maxim Integrated Products – Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA

Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
______________________________________________________________Pin Description
PIN
1, 3, 5, 7,
10, 16, 24
2
4
6
8, 9, 10
11
12
13
14
15, 23
17
18
19
20
21
22
NAME
GND
CCDIN
AIN1
AIN2
I.C.
REFGND
REF-
REF+
REFBIAS
V_DD
MODE
SCLK
DATA
LOAD
VIDSAMP
CLAMP
FUNCTION
Ground
CCD Input. Connect CCD through a series 0.047µF capacitor (C_EXT).
Auxiliary Analog Input Channel 1
Auxiliary Analog Input Channel 2
Internally Connected. Do not connect to this pin.
Reference Ground. Ground reference for all analog signals.
Lower Limit of Reference Span. Sets the zero-code voltage. Range is GND ≤ REF- ≤ REF+.
Nominally 0.5V.
Upper Limit of Reference Span. Sets the full-scale input. Voltage range is REF- ≤ REF+ ≤ V_DD.
Nominally 3.0V.
Reference Power Supply. Connect to external +5.0V to set V_REF+ to +3.0V and V_REF- to +0.5V.
Power Supply, +5V. Bypass to ground very close to the device and connect the two pins together,
close to the MAX1101.
Control Input. Set high, DATA is an output of the ADC. Set low, DATA enables programming of the
PGA and mux.
Serial Clock Input
Data Input or Output, as controlled by MODE
Control Input. Loads serial shift-register data to PGA and multiplexer registers when MODE = 0.
Control Input. Samples the video level and initiates the ADC conversion.
Control Input. Samples black level. Can be used for correlated double sampling.
AIN2
AIN1
CCDIN
CLAMP
CIRCUIT
CLAMP
PGA
GAIN
6
2
1
MUX ADC
0
2
REFBIAS
REF+
8
REF-
REFGND
VIDSAMP
REGISTER
6
REGISTER
2
Figure 1. MAX1101 Functional Diagram
REGISTER
8
SERIAL
PORT
DATA
SCLK
LOAD
MODE
_______________Detailed Description
Overview
The MAX1101 directly processes the pixel stream from
a monochrome CCD, and removes black level, offset,
and noise errors through an internal clamp circuit,
which can be used as a correlated double sampler
(CDS). It uses a 6-bit, programmable-gain amplifier
(PGA) to adjust gain. A three-input multiplexer (mux)
selects either the PGA output or two unassigned inputs
(AIN1, AIN2). The processed analog signal is digitized
by an 8-bit, half-flash analog-to-digital converter (ADC),
and output serially through the DATA pin.
Digital data is input and output through the bidirectional
serial pin (DATA) synchronously with the external serial
clock (SCLK). When MODE = 0, the mux channels and
the PGA gain can be programmed via DATA. With MODE
= 1 (high), ADC serial data is output through this pin.
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