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MAX1464 Datasheet, PDF (5/47 Pages) Maxim Integrated Products – Low-Power, Low-Noise Multichannel Sensor Signal Processor
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
ELECTRICAL CHARACTERISTICS (continued)
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF = VSS = 0V,
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
LARGE OP AMP
Input Offset Voltage
Input Bias Current
SYMBOL
VOS_LG
IB_LG
CONDITIONS
MIN TYP MAX UNITS
0
±6
mV
±225
nA
DC Gain
AVOL_LG
OUTnLG = 0.5V to 4.5V (n = 1 or 2),
RLOAD = ∞
100
dB
Gain Bandwidth Product
Slew Rate
Common-Mode Input Range
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Input-Referred Noise Voltage
GBW_LG
SR_LG
CMR_LG
CMRR_LG
PSRR_LG
VN_LG
Output-Voltage High
VOH_LG
Output-Voltage Low
VOL_LG
Output Source Current
ISRC_LG
Output Sink Current
Maximum Output Load
Capacitance
ISNK_LG
CL_LG
OP-AMP SWITCH
Analog Signal Range
VSW
On-Resistance
RON
Off-Isolation
VISO
DIGITAL-TO-ANALOG CONVERTER
Resolution
RESDAC
Integral Nonlinearity
INLDAC
Differential Nonlinearity
DNLDAC
AVOL_LG = +1V/V
AVOL_LG = +1V/V
VCM OPAMP = VSS to VDD
At DC
0.1Hz to 1kHz
0.1Hz to 1MHz
RLOAD = ∞
RLOAD = 1kΩ to VSS
RLOAD = ∞
RLOAD = 1kΩ to VDD
VOUTnLG = VOH_LG, RLOAD = 1kΩ to VSS
VOUTnLG = VOL_LG, RLOAD = 1kΩ to VDD
RLOAD = ∞, phase margin > 55°
Offset Error
VDAC OS DAC ref = VDD, DAC data = 0000h
Bit Weight
Power-Supply Rejection
Output Noise
Output Settling Time
PULSE-WIDTH MODULATOR
Resolution
Period
BWDAC
PSRDAC
ONDAC
STDAC
DAC ref = 5VDC
At DC, DAC ref = VREF
DAC buffer is the small op amp
To 0.1% of final value
RESPWM (Note 6)
PPWM fCLK = 4.0MHz
4.0
3.2
VSS + 0.02
VDD - 0.02
70
70
19
160
VDD - 0.1
VDD - 0.125
0.03
0.13
-4.9
4.9
MHz
V/µs
V
dB
dB
µVRMS
V
V
mA
mA
200
pF
VSS
VDD
V
5
kΩ
80
dB
VDD / 2
- 0.06
16
3
±1
91.55
0.02
±3
250
VDD / 2
+ 0.06
Bits
Bits
Bits
V
µV/LSB
%FS
LSB
µs
12
Bits
8.192
ms
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