MAX1464 Datasheet, PDF (38/47 Pages) Maxim Integrated Products – Low-Power, Low-Noise Multichannel Sensor Signal Processor

Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Table 28. GPIO1_Control (Address = 40h)
BITS
15–6
5
4
3
2
1
0
NAME
—
OUT1
EN1
IN1
CLR1
INV1
EDGE1
DESCRIPTION
Unused.
OUT1 value is driven onto the GPIO1 pin when the output driver is enabled.
Enable the output driver; 1 = enabled, 0 = disabled, and OUT tri-stated.
When EDGE1 = 0: The value input on GPIO1 is clocked into this bit (Notes 14, 15).
When EDGE1 = 1: An edge detection on GPIO1 causes a 1 to be clocked into this bit.
Clear IN1 bit; 1 = clear IN1 to 0, 0 = IN1 retains its status (Note 16).
When EDGE1 = 0: Invert the logic value IN1; 1 = invert input, 0 = do not invert. When EDGE1 = 1: Select
edge capture type; 1 = falling edge detect; 0 = rising edge detect.
Select level or edge detection at IN1; 1 = detect edges, 0 = detect and track logic levels.
Table 29. GPIO2_Control (Address = 41h)
BITS
15–6
5
4
3
2
1
0
NAME
—
OUT2
EN2
IN2
CLR2
INV2
EDGE2
DESCRIPTION
Unused.
OUT2 value is driven onto the GPIO2 pin when the output driver is enabled.
Enable the output driver; 1 = enabled, 0 = disabled, and OUT tri-stated.
When EDGE2 = 0: The value input on GPIO2 is clocked into this bit (Notes 14, 15).
When EDGE2 = 1: An edge detection on GPIO2 causes a 1 to be clocked into this bit.
Clear IN2 bit; 1 = clear IN2 to 0, 0 = IN2 retains its status (Note 16).
When EDGE2 = 0: Invert the logic value IN2; 1 = invert input, 0 = do not invert. When EDGE2 = 1: Select
edge capture type; 1 = falling edge detect; 0 = rising edge detect.
Select level or edge detection at IN2; 1 = detect edges, 0 = detect and track logic levels.
Note 14: A pulse or level must remain on GPIOn for four periods of f_OSC to be latched into IN.
Note 15: The CLRn bit must be cleared to zero to reenable GPIO to value tracking.
Note 16: The CLRn bit must be cleared to zero to reenable GPIO edge detection.
Table 30. TMR_Control (Address = 20h)
BIT
15
14
13–1
0
NAME
TMDN
TMEN
—
ENAHALT
DESCRIPTION
Timer done bit set by the counter; 1 = timeout value reached, 0 = timeout not reached. Read-only
bit.
Timer enable bit; A 1 written to TMEN resets TMDN to zero and starts counter. TMEN is reset to
zero by the counter when timeout value is reached.
Unused.
Enable CPU halt; 1 = CPU halted for duration of timer interval, 0 = CPU not halted.
Table 31. TMR_Config (Address = 21h)
BIT
15–12
11–0
NAME
PS[3:0]
TO[11:0]
DESCRIPTION
Prescaler setting to use during the timing interval. PS[3 ] = MSB.
Timeout value to use during the timing interval. TO[11] = MSB.
38 ______________________________________________________________________________________