MAX1464 Datasheet, PDF (16/47 Pages) Maxim Integrated Products – Low-Power, Low-Noise Multichannel Sensor Signal Processor

Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Coarse-Input Offset Adjustment
Differential input signals that have an offset can be par-
tially nulled by the input coarse-offset (CO) DAC. An off-
set voltage is added to the input signal prior to gaining
the signal. This allows a maximum gain to be applied to
the differential input signal without saturating the conver-
sion channel. The CO signal added to the differential sig-
nal is a percentage of the full-scale ADC reference
voltage as referred to the ADC inputs. Low PGA gain set-
tings add smaller amounts of coarse offset to the differ-
ential input. Large PGA gain settings enable cor-
respondingly larger amounts of coarse offset to be
added to the input signal. The CO DAC also applies to
the temperature channel enabling offset compensation
of the temperature signal. See Table 18.
Bias Current Settings
The analog circuitry within the ADC module operates
from a current bias setting that is programmable. The
programmable levels of operation are fractions of the
full bias current. The operating power consumption of
the ADC can be reduced at the penalty of increased
conversion times that may be desirable in very-low-
power applications. It is recommended operating the
ADC at full bias when possible. The amount of bias as
a fraction of full bias is shown in Table 19. The setting is
controlled by the BIASn[2:0] bits in the ADC_config_nb
registers where n = 1, 2, or T.
Reference Input Voltage Select
The ADC can use one of three different reference volt-
age inputs depending on the conversion channel and
REFn setting as shown in Table 20. The differential
inputs can be converted ratiometrically to the supply
voltage (V_DD), converted ratiometrically to an externally
supplied voltage at V_REF, or converted nonratiometri-
cally using a fixed voltage source derived from the
internal bandgap voltage source. The temperature
channel is always converted using the internal bandgap-
derived voltage source and therefore is not selectable.
Output Sample Rate
Generally, the sensor and temperature data are convert-
ed and calculated by an algorithm in the execution loop.
The output sample rate of the data depends on the con-
version time, the CPU algorithm loop time, and the time to
store the result in the DOPn_DATA register. To achieve
uniform sampling, the instruction code must be written to
provide a consistent algorithm loop time, including
branch instruction variations. This total loop time interval
should be repeatable for a uniform output rate.
The MAX1464 has a built-in timer that can be used to
ensure that the sampling interval is uniform. The timeout
value can be set so the CPU computations and the read-
ing of the serial interface, if required, can be completed
before timeout. The GPIO pins can be utilized to interrupt
an external master microcontroller when the ADC con-
version is done and/or when the CPU computations are
done so the serial interface can be read quickly.
DAC, Op Amp, PWM Modules (DOPn)
There are two output modules in the MAX1464—DOP1
and DOP2 (Figure 5). Each of the DOP modules con-
tains a 16-bit DAC, a 12-bit digital PWM converter, a
small op amp, and a large op amp with high-output-
drive capability. Switches in the DOP module enable a
range of interconnectivity among the converters, op
amps, and the external pins. Either the DAC or the
PWM can be selected as the primary output signal. The
DAC output signal is routed to one of the op amps and
made available to a device pin. The signal-switching
arrangement also allows the unused op amp to be con-
figured as an uncommitted device with all connections
available to external pins.
The DAC and op amps have a power-control bit in the
power module. When power is disabled, all circuits in
the DAC and the op amp are disabled with inputs and
outputs in a tri-state condition. The proper bits in the
power module must be enabled for operation of the
DAC and op amps.
The DAC input is a 16-bit two’s-complement value. An
input value of 0000h produces an output voltage of one
half the DAC reference voltage. The DAC output voltage
increases for positive two’s-complement numbers, and
decreases for negative two’s-complement numbers.
The PWM input is a 12-bit two’s complement value. It
shares the same input register (DOPn_Data) as the
DAC, using the 12 MSBs of the 16-bit register. An input
value of 000Xh produces a 50% duty cycle waveform at
the output. The PWM output duty cycle increases for
positive two’s-complement numbers, and decreases for
negative two’s-complement numbers.
DOP_n Configuration Options
Each of the DOP modules can be configured in several
different modes to suit a wide range of output signal
requirements. The Functional Diagram shows the various
switch settings of the configuration and control registers.
In situations where configuration settings create a con-
flict in switch activation, a priority is applied to the switch
logic to prevent the conflict.
The DAC and/or the PWM can be selected as the out-
put signal source. The DAC output signal is routed to
one of the op amps and made available to a device
pin. Selecting the large op amp as the DAC output dri-
ver device enables a robust current drive capability for
driving signals into low-impedance loads or across
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