MAX1464 Datasheet, PDF (15/47 Pages) Maxim Integrated Products – Low-Power, Low-Noise Multichannel Sensor Signal Processor

Low-Power, Low-Noise Multichannel
Sensor Signal Processor
REF
INP1
INM1
INP2
INM2
M
U
PGA
X
V_SS
TEMPERATURE
SENSOR
NO.
SINGLE-ENDED
1
V_BG
2 OUTnSM
3 OUTnLG
4
V_DD
5
V_SS
6 DACnOUT VIA OUTnSM
7 DACnOUT VIA OUTnLG
8 INPn
9 INMn
V_DD
2 x V_REF
4 x V_BG
VBG
00h
ADC_Control
01h
ADC_Data_1
02h
ADC_Config_1A
03h
ADC_Config_1B
ADC
04h
ADC_Data_2
05h
ADC_Config_2A
06h
ADC_Config_2B
07h
ADC_Data_T
08h
ADC_Config_TA
09h
ADC_Config_TB
Figure 4. ADC Module
Single-ended inputs can be converted by either channel
1 or 2 by initiating a conversion on the appropriate chan-
nel with the SE[3:0] bits set to the desired single-ended
input (Table 7). Several of the single-ended signals are
converted with a fixed gain. The reduced gain of 0.7V/V
allows signals at or near the supply rails to be converted
without concern of saturation. Other single-ended signals
can be converted with the full selectable PGA gain range.
Programmable-Gain Amplifier
The gain of the differential inputs and several
single-ended inputs can be set to values between
0.99V/V to 244V/V as shown in Table 14. The PGA bits
are set in ADC_Config_nA where n = 1, 2, or T. The gain
setting must be selected prior to initiating a conversion.
ADC Conversion Time and Resolution
The ADC conversion time is a function of the selected
resolution, ADC clock (f_ADC), and system clock frequen-
cy (f_CLK). The resolution can be selected from 9 bits to 16
bits in the ADC_Config_nA (where n = 1, 2, or T) register
by bits RESn[2:0]. The lower resolution settings (9 bit)
convert faster than the higher resolution settings (16 bit).
The ADC clock f_ADC is derived from the primary system
clock f_CLK by a prescalar divisor. The divisor can be set
from 4 to 512, producing a range of f_ADC from 1MHz
down to 7.8125kHz when f_CLK is operating at 4.0MHz.
Other values of f_CLK produce other scaled values of
f_ADC. See Tables 15 and 16.
Systems operating with very low power consumption
benefit from the reduced f_ADC clock rate. Slower clock
speeds require less operating current. Systems operat-
ing from a larger power consumption budget can use
the highest f_ADC clock rate to improve speed perfor-
mance over power performance.
The ADC conversion times for various resolution and
clock-rate settings are summarized in Table 17. The
conversion time is calculated by the formula:
t_CONVERT = (no. of f_ADC clocks per conversion) /
f_ADC
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