MAX1464 Datasheet, PDF (25/47 Pages) Maxim Integrated Products – Low-Power, Low-Noise Multichannel Sensor Signal Processor

Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PC-register ← PC-register + 1 (point to next
instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit logical NOT operation on the contents
of the X-register. Each bit is flipped to its complemen-
tary value. The result is stored back into the X-register.
The previous contents of X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is not preserved.
No branching occurs.
No other registers are affected.
BPX
Branch If Positive Or Zero
Op-code:
1011 XXXX_BINARY BXh
Operation:
If MSB(Register I) = 0 then:
PC-register ← PC-register + X-register
Else:
PC-register ← PC + 1 (point to next
instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit check of I-register for a positive (two’s
complement) or zero value and branch the number of
instructions indicated in register-X. The test operation
checks the most significant bit, bit-15, for a 0_B and, if
true, adds the contents of the X-register to the program
counter register. This causes an immediate jump to the
new program memory location. The next instruction to
execute is fetched from the program memory byte
pointed to by the new contents of the PC-register.
A 1_B in bit-15 of the I-register is indicative of a negative
number (two’s complement) to which the test for posi-
tive-or-zero value fails. This causes the “else” operation
to be performed and the PC-register is incremented by
one pointing to the next sequential instruction in pro-
gram memory to be executed. The effect bypasses the
branch mechanism and normal, sequential, code exe-
cution results.
The next instruction to execute is fetched from the pro-
gram memory byte pointed to by the new contents of
the PC-register. The previous contents of the PC-regis-
ter are overwritten and lost.
Two’s-complement data format is preserved.
Branching may occur.
No other registers are affected.
BNX
Branch If Not Zero
Op-code:
1100 XXXX_BINARY CXh
Operation:
If I-register ≠ 0000h then:
PC-register ← PC-register + X-register
Else:
PC-register ← PC-register + 1 (point to
next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit check of the I-register for a nonzero
condition and, if true, add the contents of the X-register
to the program pointer register. This causes an immedi-
ate jump to the new program memory location. The
next instruction to execute is fetched from the program
memory byte pointed to by the new contents of the PC-
register.
A 1_B in any bit of the I-register is indicative of a nonzero
number to which the test for a zero value fails. This
causes the “else” operation to be performed and the
PC-register is incremented by one pointing to the next
sequential instruction in program memory to be execut-
ed. The effect bypasses the branch mechanism and
normal, sequential, code execution results.
The next instruction to execute is fetched from the pro-
gram memory byte pointed to by the new contents of
the PC-register. The previous contents of the PC-regis-
ter are overwritten and lost.
Two’s-complement data format is preserved.
Branching may occur.
No other registers are affected.
RDX
Read Port X
Op-code:
1101XXXX_BINARY DXh
Operation:
A-register ← port-X
PC-register ← PC + 1 (point to next instruction)
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