MAX13101E Datasheet, PDF (5/18 Pages) Maxim Integrated Products – 16-Channel Buffered CMOS Logic-Level Translators

16-Channel Buffered CMOS
Logic-Level Translators
Test Circuits/Timing Diagrams
V_L
SOURCE
MAX13101E
MAX13102E
MAX13103E
MAX13108E
EN/(MULT)
6kΩ
I/O V_{L_}
6kΩ
R_S
V_CC
I/O V_{CC_}
C_{I/OVCC_}
I/O V_{L_}
90%
50%
10%
I/O V_{CC_}
90%
50%
10%
t_RISE/FALL ≤ 3ns
t_PHL
50%
t_PLH
90%
10%
ALL UNUSED I/O V_{CC_} AND I/O V_{L_} CONNECTED TO GND
( ) ARE FOR THE MAX13108E
Figure 1a. Driving I/O V_{L_}
t_PVL-VCC = t_PHL or t_PLH
t_FVCC
t_RVCC
Figure 1b. Timing for Driving I/O V_{L_}
V_L
I/O V_{L_}
C_{I/OVL_}
MAX13101E
MAX13102E
MAX13103E
MAX13108E
EN/(MULT)
6kΩ
6kΩ
V_CC
R_S
I/O V_{CC_}
SOURCE
ALL UNUSED I/O V_{CC_} AND I/O V_{L_} CONNECTED TO GND
( ) ARE FOR THE MAX13108E
Figure 2a. Driving I/O V_{CC_}
I/O V_{CC_}
90%
50%
10%
I/O V_{L_}
90%
50%
10%
t_RISE/FALL ≤ 3ns
t_PHL
t_FVL
t_PVCC-VL = t_PHL or t_PLH
Figure 2b. Timing for Driving I/O V_{CC_}
50%
t_PLH
90%
10%
t_RVL
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