MAX13101E Datasheet, PDF (4/18 Pages) Maxim Integrated Products – 16-Channel Buffered CMOS Logic-Level Translators

16-Channel Buffered CMOS
Logic-Level Translators
TIMING CHARACTERISTICS
(V_CC = +1.65V to +5.5V, V_L = +1.2V to V_CC, EN = V_L (MAX13101E/MAX13102E/MAX13103E), MULT = V_L or GND (MAX13108E),
T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at V_CC = +1.65V, V_L = +1.2V, T_A = +25°C.) (Notes 1, 2)
PARAMETER
I/O V_L _ Rise Time
I/O V_L _ Fall Time
I/O V_CC_ Rise Time
I/O V_CC_ Fall Time
Propagation Delay
(Driving I/O V_L _)
Propagation Delay
(Driving I/O V_CC_)
Channel-to-Channel Skew
Part-to-Part Skew
Propagation Delay from
I/O V_L _ to I/O V_CC_ After EN
Propagation Delay from
I/O V_CC_ to I/O V_L _ After EN
Maximum Data Rate
SYMBOL
CONDITIONS
MIN
t_RVL
R_S = 50Ω, C_{I/OVL_} = 15pF, t_RISE ≤ 3ns,
(Figures 2a, 2b)
t_FVL
R_S = 50Ω, C_{I/OVL_} = 15pF, t_FALL ≤ 3ns,
(Figures 2a, 2b)
t_RVCC
R_S = 50Ω, C_{I/OVCC_} = 50pF, t_RISE ≤ 3ns,
(Figures 1a, 1b)
t_FVCC
R_S = 50Ω, C_{I/OVCC_} = 50pF, t_FALL ≤ 3ns,
(Figures 1a, 1b)
t_PVL-VCC
R_S = 50Ω, C_{I/OVCC_} = 50pF, t_RISE ≤ 3ns,
(Figures 1a, 1b)
t_PVCC-VL
R_S = 50Ω, C_{I/OVL_} = 15pF, t_RISE ≤ 3ns,
(Figures 2a, 2b)
t_SKEW
R_S = 50Ω, C_{I/OVCC_} = 50pF, C_{I/OVL_} =
15pF, t_RISE ≤ 3ns
t_PPSKEW
R_S = 50Ω, C_{I/OVCC_} = 50pF, C_{I/OVL_} =
15pF, t_RISE ≤ 3ns, ΔT_A = +20°C (Notes 3, 4)
t_EN-VCC C_{I/OVCC_} = 50pF (Figure 3)
TYP MAX UNITS
15
ns
15
ns
15
ns
15
ns
20
ns
20
ns
5
ns
10
ns
1
µs
t_EN-VL C_{I/OVL_} = 15pF (Figure 4)
R_SOURCE = 50Ω, C_{I/OVCC_} = 50pF,
C_{I/OVL_} = 15pF, t_RISE ≤ 3ns
20
1
µs
Mbps
Note 1: All units are 100% production tested at T_A = +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: For normal operation, ensure that V_L < (V_CC + 0.3V). During power-up, V_L > (V_CC + 0.3V) does not damage the device.
Note 3: V_CC from device 1 must equal V_CC of device 2. V_L from device 1 must equal V_L of device 2.
Note 4: Guaranteed by design, not production tested.
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