MAX13101E Datasheet, PDF (1/18 Pages) Maxim Integrated Products – 16-Channel Buffered CMOS Logic-Level Translators

19-3802; Rev 3; 6/08
16-Channel Buffered CMOS
Logic-Level Translators
General Description
Features
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-bit bidirectional CMOS logic-level translators pro-
vide the level shifting necessary to allow data transfer in
multivoltage systems. These devices are inherently
bidirectional due to their design and do not require the
use of a direction input. Externally applied voltages,
V_CC and V_L, set the logic levels on either side of the
devices. Logic signals present on the V_L side of the
device appear as a higher voltage logic signal on the
V_CC side of the device, and vice-versa.
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when low, reduces the V_CC and
V_L supply currents to less than 2µA. The MAX13108E
features a multiplexing input (MULT) that selects one
byte between the two, thus allowing multiplexing of the
signals. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E have ±15kV ESD protection on the I/O V_CC
side for greater protection in applications that route sig-
nals externally. Three different output configurations are
available during shutdown, allowing the I/O on the V_CC
side or the V_L side to be put in a high-impedance state
or pulled to ground through an internal 6kΩ resistor.
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
accept V_CC voltages from +1.65V to +5.5V and V_L
voltages from +1.2V to V_CC, making them ideal for data
transfer between low-voltage ASICs/PLDs and higher
voltage systems. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E are available in 36-bump
WLP and 40-pin TQFN packages, and operate over the
extended -40°C to +85°C temperature range.
♦ Wide Supply Voltage Range
V_CC Range of 1.65V to 5.5V
V_L Range of 1.2V to V_CC
♦ ESD Protection on I/O V_CC Lines
±15kV Human Body Model
♦ Up to 20Mbps Throughput
♦ Low 0.03µA Typical Quiescent Current
♦ WLP and TQFN Packages
Pin Configurations
TOP VIEW OF BOTTOM LEADS
30 29 28 27 26 25 24 23 22 21
I/O V_CC4 31
I/O V_CC3 32
20 ^{I/O V}CC¹³
19 ^{I/O V}CC¹⁴
I/O V_CC2 33
18 ^{I/O V}CC¹⁵
I/O V_CC1 34
V_CC 35
V_L 36
MAX13101E
MAX13102E
MAX13103E
17 ^{I/O V}CC¹⁶
16 VCC
15 VL
I/O V_L1 37
14 I/O VL16
I/O V_L2 ₃₈
*EP
I/O V_L3 ₃₉
I/O V_L4 ₄₀ ⁺
13 I/O VL15
12 I/O VL14
11 I/O VL13
1 2 3 4 5 6 7 8 9 10
CMOS Logic-Level
Translation
Portable Equipment
Cell Phones
Applications
PDAs
Digital Still Cameras
Smart Phones
*EXPOSED PAD CONNECTED TO GROUND
TQFN
Pin Configurations continued at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
Ordering Information/Selector Guide
PART
PIN-PACKAGE
DATA
I/O V_L STATE
RATE (Mbps) DURING SHUTDOWN
MAX13101EEWX+*
36 WLP**
3.06mm x 3.06mm
20
High impedance
MAX13101EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20
High impedance
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes a lead-free/RoHS-compliant package.
*Future product—contact factory for availability.
**WLP bumps are in a 6 x 6 array.
***EP = Exposed pad.
Ordering Information/Selector Guide continued at end of data sheet.
I/O V_CC STATE
DURING SHUTDOWN
6kΩ to GND
6kΩ to GND
MULTIPLEXER
FEATURE
No
No
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