MAX13101E Datasheet, PDF (16/18 Pages) Maxim Integrated Products – 16-Channel Buffered CMOS Logic-Level Translators

16-Channel Buffered CMOS
Logic-Level Translators
Ordering Information/Selector Guide (continued)
PART
PIN-PACKAGE
DATA
I/O V_L STATE
RATE (Mbps) DURING SHUTDOWN
MAX13102EEWX+
36 WLP**
3.06mm x 3.06mm
20
6kΩ to GND
MAX13102EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20
6kΩ to GND
MAX13103EEWX+
36 WLP**
3.06mm x 3.06mm
20
High impedance
MAX13103EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20
High impedance
36 WLP**
MAX13108EEWX+ _{3.06mm x 3.06mm}
20
High impedance
MAX13108EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20
High impedance
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes a lead-free/RoHS-compliant package.
**WLP bumps are in a 6 x 6 array.
***EP = Exposed pad.
I/O V_CC STATE
DURING SHUTDOWN
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
MULTIPLEXER
FEATURE
No
No
No
No
Yes
Yes
TOP VIEW OF BOTTOM LEADS
Pin Configurations (continued)
30 29 28 27 26 25 24 23 22 21
I/O V_CC4 31
I/O V_CC3 32
20 ^{I/O VCC13}
19 ^{I/O V}CC¹⁴
I/O V_CC2 33
18 ^{I/O V}CC¹⁵
I/O V_CC1 34
17 ^{I/O V}CC¹⁶
V_CC 35
MA131018E
16 VCC
V_L 36
15 VL
I/O V_L1 37
14 I/O VL16
I/O V_L2 ₃₈
*EP
I/O V_L3 ₃₉
I/O V_L4 ₄₀ +
13 I/O VL15
12 I/O VL14
11 ^{I/O V}L¹³
1 2 3 4 5 6 7 8 9 10
* EXPOSED PAD CONNECTED TO GROUND
TQFN
16 ______________________________________________________________________________________