MAX13101E Datasheet, PDF (13/18 Pages) Maxim Integrated Products – 16-Channel Buffered CMOS Logic-Level Translators

16-Channel Buffered CMOS
Logic-Level Translators
Detailed Description
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
logic-level translators provide the level shifting neces-
sary to allow data transfer in a multivoltage system.
Externally applied voltages, V_CC and V_L, set the logic
levels on either side of the device. Logic signals pre-
sent on the V_L side of the device appear as a higher
voltage logic signal on the V_CC side of the device, and
vice-versa. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E are bidirectional level translators allowing
data translation in either direction (V_L ↔V_CC) on
any single data line. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E accept V_L from +1.2V to V_CC.
All devices have a V_CC range from +1.65V to +5.5V,
making them ideal for data transfer between low-volt-
age ASICs/PLDs and higher voltage systems.
The MAX13101E/MAX13102E/MAX13103E feature an
output enable mode that reduces V_CC supply current to
less than 1µA, and V_L supply current to less than 2µA
when in shutdown. The MAX13108E features a multi-
plexing input that selects one byte between the two,
thus allowing multiplexing of the signals. The
MAX13101E/MAX13102E/MAX13103E/MAX13108E
have ±15kV ESD protection on the I/O V_CC side for
greater protection in applications that route signals
externally. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E operate at a guaranteed data rate of
20Mbps. The maximum data rate depends heavily
on the load capacitance (see the Typical Operating
Characteristics) and the output impedance of the
external driver.
Power-Supply Sequencing
For proper operation, ensure that +1.65V ≤ V_CC ≤ +5.5V,
+1.2V ≤ V_L ≤ +5.5V, and V_L ≤ V_CC. During power-up
sequencing, V_L ≥ V_CC does not damage the device.
When V_CC is disconnected and V_L is powering up, up to
10mA of current can be sourced to each load on the V_L
side, yet the device does not latch up. To guarantee that
no excess leakage current flows and that the device
does not interfere with the I/O on the V_L side, V_CC should
be connected to GND with a max 50Ω resistor when the
V_CC supply is not present (Figure 5).
Input Driver Requirements
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
architecture is based on a one-shot accelerator output
stage (Figure 6). Accelerator output stages are always
in tri-state except when there is a transition on any of
the translators on the input side, either I/O V_L_ or
I/O V_CC_. Then a short pulse is generated, during
which the accelerator output stages become active and
charge/discharge the capacitances at the I/Os. Due to
V_BATT
DISABLE
V_CC SUPPLY
+1.2V TO +5.5V
R_DSON < 50Ω
V_CC
V_L
MAX13101E
MAX13102E
MAX13103E
MAX13108E
I/O V_CC1
I/O V_L1
I/O V_CC16
I/O V_L16
GND
Figure 5. Recommended Circuit for Powering Down V_CC
the bidirectional nature, both input stages become
active during the one-shot pulse. This can lead to some
current feeding into the external source that is driving
the translator. However, this behavior helps to speed
up the transition on the driven side.
For proper full-speed operation, the output current of a
device that drives the inputs of the MAX13101E/
MAX13102E/MAX13103E/MAX13108E should meet the
following requirement:
i > 10⁸ x V x (C + 10pF)
where, i is the driver output current, V is the logic-supply
voltage (i.e., V_L or V_CC) and C is the parasitic capaci-
tance of the signal line.
Enable Output Mode (EN)
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when driven low, places the
device into shutdown mode. During shutdown, the
MAX13101E I/O V_CC_ ports are pulled down to ground
with internal 6kΩ resistors and the I/O V_L _ ports enter
tri-state. MAX13102E I/O V_CC_ lines enter tri-state and
the I/OV_L _ lines are pulled down to ground with internal
6kΩ resistors. All I/O V_CC_ and I/O V_L _ lines on the
MAX13103E enter tri-state while the device is in shut-
down mode. During shutdown, the V_CC supply current
reduces to less than 1µA, and the V_L supply current
reduces to less than 2µA. To guarantee minimum shut-
down supply current, all I/O V_L _ need to be driven to
GND or V_L, or pulled to GND or V_L through 100kΩ
resistors. All I/O V_CC_ need to be driven to GND or
V_CC, or pulled to GND or V_CC through 100kΩ resistors.
Drive EN to logic-high (V_L or V_CC) for normal operation.
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