MAX11156 Datasheet, PDF (5/27 Pages) Maxim Integrated Products – 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN

MAX11156
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
Electrical Characteristics (continued)
(V_DD = 4.75V to 5.25V, V_OVDD = 2.3V to 5.25V, f_SAMPLE = 500kHz, V_REF = 4.096V, Reference Mode 3; T_A = T_MIN to T_MAX, unless
otherwise noted. Typical values are at T_A = +25NC.) (Note 2)
PARAMETER
Output Voltage Low
Three-State Leakage Current
Three-State Output Capacitance
TIMING (Note 9)
Time Between Conversions
Conversion Time
Acquisition Time
CNVST Pulse Width
SCLK Period (CS Mode)
SCLK Period (Daisy-Chain
Mode)
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Valid
Delay
CNVST Low to DOUT D15 MSB
Valid (CS Mode)
CNVST High or Last SCLK
Falling Edge to DOUT High
Impedance
SYMBOL
V_OL
t_CYC
t_CONV
t_ACQ
t_CNVPW
t_SCLK
t_SCLK
t_SCLKL
t_SCLKH
t_DDO
t_EN
t_DIS
CONDITIONS
I_SINK = 2mA
CNVST rising to data available
t_ACQ = t_CYC - t_CONV
CS mode
V_OVDD > 4.5V
V_OVDD > 2.7V
V_OVDD > 2.3V
V_OVDD > 4.5V
V_OVDD > 2.7V
V_OVDD > 2.3V
V_OVDD > 4.5V
V_OVDD > 2.7V
V_OVDD > 2.3V
V_OVDD > 2.7V
V_OVDD < 2.7V
CS Mode
MIN
TYP
MAX
UNITS
0.4
V
-10
+10
µA
15
pF
2
100000
µs
1.35
1.5
µs
0.5
µs
5
ns
14
20
ns
26
16
24
ns
30
5
ns
5
ns
12
18
ns
23
14
ns
17
20
ns
V_OVDD > 4.5V
3
DIN Valid Setup Time from SCLK
Falling Edge
t_SDINSCK
V_OVDD > 2.7V
5
ns
V_OVDD > 2.3V
6
DIN Valid Hold Time from SCLK
Falling Edge
t_HDINSCK
0
ns
SCLK Valid Setup Time to
CNVST Falling Edge
t_SSCKCNF
3
ns
SCLK Valid Hold Time to CNVST
Falling Edge
t_HSCKCNF
6
ns
www.maximintegrated.com
Maxim Integrated │  5