MAX11156 Datasheet, PDF (12/27 Pages) Maxim Integrated Products – 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN

MAX11156
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
Overvoltage Input Clamps
The MAX11156 includes an input clamping circuit that
activates when the input voltage at AIN+ is above (V_DD
+ 300mV) or below -(V_DD + 300mV). The clamp circuit
remains high impedance while the input signal is within
the range of Q(V_DD + 100mV) and draws little to no cur-
rent. However, when the input signal exceeds this range
the clamps begin to turn on. Consequently, to obtain the
highest accuracy, ensure that the input voltage does not
exceed the range of Q(V_DD + 100mV).
To make use of the input clamps, connect a resistor (R_S)
between the AIN+ input and the voltage source to limit the
voltage at the analog input and to ensure the fault current
into the devices does not exceed Q20mA. Note that the
voltage at the AIN+ input pin limits to approximately 7V
during a fault condition so the following equation can be
used to calculate the value of R_S:
R_S
=
V_{FAULT MAX}
20mA
−
7V
where V_FAULTMAX is the maximum voltage that the
source produces during a fault condition.
Figure 1 and Figure 2 illustrate the clamp circuit volt-
age current characteristics for a source impedance
R_S = 1280I. While the input voltage is within the Q(V_DD
+ 300mV) range, no current flows in the input clamps.
Once the input voltage goes beyond this voltage range,
the clamps turn on and limit the voltage at the input pin.
Internal/External Reference
(REFIO) Configuration
The MAX11156 includes a standard SPI interface that
selects internal or external reference modes of opera-
tion through an input configuration register (see the
Input Configuration Interface section). The MAX11156
features an internal bandgap reference circuit (V_REFIO =
4.096V) that is buffered with an internal reference buffer
that drives the REF pin. The MAX11156 configure regis-
ter allows four combinations of reference configuration.
These reference mode are:
Reference Mode 00: ADC reference is provided by the
internal bandgap feed out the REFIO pin, noise filtered
with an external capacitor on the REFIO pin, then buff-
ered by the internal reference buffer and decoupled with
an external capacitor on the REF pin. In this mode the
ADC requires no external reference source.
Reference Mode 01: ADC reference is provided exter-
nally and feeds into the REFIO pin, buffered with the
internal reference buffer and decoupled with an external
capacitor on the REF pin. This mode is typically used
when a common reference source is needed for more
than one MAX11156.
Reference Mode 10: The internal bandgap is used as a
reference source output and feed out to the REFIO pin.
However, the internal reference buffer is in a shutdown
state and the REF pin is high impedance. This state
would typically be used to provide a common reference
source to a set of external reference buffers for several
MAX11156.
MAX11156 INPUT CLAMP
CHARACTERISTICS
25
AIN+ PIN
20
INPUT SOURCE
15
10
5
0
-5
-10
-15
-20
R_S = 1280I
VDD = 5.0V
-25
-40 -30 -20 -10 0 10 20 30 40
SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V)
Figure 1. Input Clamp Characteristics
MAX11156 INPUT CLAMP
CHARACTERISTICS
25
AIN+ PIN
20
INPUT SOURCE
15
10
5
0
-5
-10
-15
-20
RS = 1280I
VDD = 5.0V
-25
-8 -6 -4 -2 0 2 4 6 8
SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V)
Figure 2. Input Clamp Characteristics (Zoom In)
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