MAX11156 Datasheet, PDF (19/27 Pages) Maxim Integrated Products – 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN

MAX11156
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
CNVST
tCNVPW
tCYC
DIN
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSSCKCNF
SCLK
tSCLK
tHSCKCNF
tSCLKL
1
2
3
4
17
18
19
tSCLKH
tDDO
tDIS
DOUT
BUSY BIT
D17
D16
D15
D1
D0
Figure 9. CS With Busy Indicator Mode Timing
When the conversion is complete, DOUT transitions from
high impedance to a low logic level, signaling to the digital
host through the interrupt input that data readback can
commence. The MAX11156 then enters the acquisition
phase. The data bits are then clocked out, MSB first, by
subsequent SCLK falling edges. DOUT returns to high
impedance after the 19th SCLK falling edge or when
CNVST goes high, and is then pulled to OVDD through
the external pullup resistor.
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