MAX11156 Datasheet, PDF (22/27 Pages) Maxim Integrated Products – 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN

MAX11156
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
the chain can be connected to an interrupt input on the
digital host. The digital host should insert a 50ns delay
from the receipt of this interrupt before reading out data
from all ADCs to ensure that all devices in the chain have
completed conversion.
The conversion data is stored within an internal shift reg-
ister. To read these bits out, CNVST is brought low and
each bit is shifted out on subsequent SCLK falling edge.
The DIN input of each ADC in the chain is used to transfer
conversion data from the previous ADC into the internal
shift register of the next ADC, thus allowing for data to be
clocked through the multichip chain on each SCLK falling
edge. The total of number of falling SCLKs needed to read
back all data from N ADCs is 18 × N + 1 edges, the one
additional SCLK falling edge required to clock out the busy
mode bit from the host side ADC.
In daisy-chain mode, the maximum conversion rate is
reduced due to the increased readback time. For instance,
with a 5ns digital host setup time and 3V interface, up to four
MAX11156 devices running at a conversion rate of 276ksps
can be daisy-chained on a 3-wire port.
CNVST
DIN
MAX11156 _DOUT
DA
DEVICE A
SCLK
CNVST
DIN
MAX11156 _DOUT
DEVICE B
SCLK
CONFIG
CONVERT
DIGITAL HOST
D_B
DATA IN
CLK
Figure 12. Daisy-Chain, No-Busy Indicator Mode Connection Diagram
CNVST
DIN
ACQUISITION
tCONV
CONVERSION
SCLK
DOUTB
tCNVPW
tCYC
1
DB17
tSCLKL
2
3
tDDO
16
tSCLKH
DB16 DB15
tACQ
ACQUISITION
tSCLK
17
18
19
20
DB1 DB0 DA17 DA16
tSSCKCNF
34
35
36
DA1 DA0
Figure 13. Daisy-Chain, No-Busy Indicator Mode Timing
tHSCKCNF
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