MAX11156 Datasheet, PDF (16/27 Pages) Maxim Integrated Products – 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN

MAX11156
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
CNVST
SCLK
DIN
tSSCKCNF
0
tSDINSCK
tHSCKCNF
123456701234567
tHDINSCK
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
DATA LOADED TO PART B
SHIFTED THROUGH PART A
DATA LOADED TO PART A
Figure 5. Input Configuration Timing in Daisy-Chain Mode
Configuring in Daisy-Chain Mode
Figure 5 details the configuration register load process
when the MAX11156 is connected in a daisy-chain con-
figuration (see Figure 12 and Figure 14 for hardware con-
nections). The load process is enabled on the falling edge
of CNVST when SCLK is held high. In daisy-chain mode,
the input configuration registers are chained together
through DOUT to DIN. Device A’s DOUT will drive device
B’s DIN. The input configuration register is an 8-bit, first-
in first-out shift register. The configuration data is clocked
in N times through 8 O N falling SCLK edges. After the
MAX11156 ADC in the chain is loaded with the configura-
tion byte, pull CNVST high to complete the configuration
register loading process. Figure 5 illustrates a configura-
tion sequence for loading two devices in a chain.
Data loaded into the configuration register alters the state of
the MAX11156 on the next conversion cycle after the regis-
ter is loaded. However, powering up the internal reference
buffer or stabilizing the REFIO pin voltage will take several
milliseconds to settle to 18-bit accuracy.
Shutdown Mode
The SHDN bit in the configuration register forces the
MAX11156 into and out of shutdown. Set SHDN to 0 for
normal operation. Set SHDN to 1 to shut down all internal
circuitry and reset all registers to their default state.
Output Interface
The MAX11156 can be programmed into one of four out-
put modes; CS modes with and without busy indicator and
daisy-chain modes with and without busy indicator. When
operating without busy indication, the user must exter-
nally timeout the maximum ADC conversion time before
commencing readback. When operating in one of the two
busy indication modes, the user can connect the DOUT
output of the MAX11156 to an interrupt input on the digital
host and use this interrupt to trigger the output data read.
Regardless of the output interface mode used, digital
activity should be limited to the first half of the conversion
phase. Having SCLK or DIN transitions near the sampling
instance can also corrupt the input sample accuracy.
Therefore, keep the digital inputs quiet for approximately
25ns before and 10ns after the rising edge of CNVST.
These times are denoted as t_SQ and t_HQ in all subse-
quent timing diagrams.
In all interface modes, the data on DOUT is valid on
both SCLK edges. However, the input setup time into
the receiving digital host will be maximized when data is
clocked into that digital host on the falling SCLK edge.
Doing so will allow for higher data transfer rates between
the MAX11156 and the digital host and consequently
higher converter throughput.
In all interface modes, it is recommended that the SCLK
be idled low to avoid triggering an input configuration write
on the falling edge of CNVST. If at anytime the device
detects a high SCLK state on a falling edge of CNVST, it
will enter the input configuration write mode and will write
the state of DIN on the next 8 falling SCLK edges to the
input configuration register.
In all interface modes, all data bits from a previous con-
version must be read before reading bits from a new
conversion. When reading out conversion data, if too
few SCLK falling edges are provided and all data bits
are not read out, only the remaining unread data bits
will be outputted during the next readout cycle. In such
an event, the output data in every other readout cycle
will appear to have been truncated as only the leftover
bits from the previous readout cycle are outputted.
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