MAX11156 Datasheet, PDF (20/27 Pages) Maxim Integrated Products – 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN

MAX11156
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
Multichannel CS Configuration,
Asynchronous or Simultaneous Sampling
The multichannel CS configuration is generally used when
multiple MAX11156 ADCs are connected to an SPI-
compatible digital host. Figure 10 shows the connection
diagram example using two MAX11156 devices. Figure 11
shows the corresponding timing.
Asynchronous or simultaneous sampling is possible by
controlling the CS1 and CS2 edges. In Figure 10, the
DOUT bus is shared with the digital host limiting the
throughput rate. However, maximum throughput is pos-
sible if the host accommodates each ADC’s DOUT pin
independently.
A rising edge on CNVST completes the acquisition,
initiates the conversion and forces DOUT to high
impedance. The conversion continues to completion
irrespective of the state of CNVST allowing CNVST
to be used as a select line for other devices on the
board. However, CNVST must be returned high before
the minimum conversion time for proper operation so
that another conversion is not initiated with insufficient
acquisition time and data correctly read out of the
device.
When the conversion is complete, the MAX11156 enters
the acquisition phase. Each ADC result can be read by
bringing its CNVST input low, which consequently outputs
the MSB onto DOUT. The remaining data bits are then
clocked by subsequent SCLK falling edges. For each
device, its DOUT will return to a high-impedance state
after the 18^th SCLK falling edge or when CNVST goes
high. This control allows multiple devices to share the
same DOUT bus.
CNVST
MAX11156
DEVICE A
SCLK
DOUT
DIN
Figure 10. Multichannel CS Configuration Diagram
CNVST
MAX11156
DEVICE B
SCLK
DOUT
DIN
CS2
CS1
DIGITAL HOST
CONFIG
DATA IN
CLK
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