MAX11156 Datasheet, PDF (10/27 Pages) Maxim Integrated Products – 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN

MAX11156
Pin Configuration
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
TOP VIEW
REFIO 1
REF 2
VDD ₃
AIN+ ₄
AIN- 5
GND 6
MAX11156
EP
TDFN
12 AGNDS
11 OVDD
10 DIN
9 _SCLK
8 _DOUT
7 CNVST
Pin Description
PIN NAME
I/O
1
REFIO
I/O
2
REF
I/O
3
V_DD
I
4
AIN+
I
5
AIN-
I
6
GND
I
7
CNVST
I
8
DOUT
O
9
SCLK
I
10
DIN
I
11
OVDD
I
12 AGNDS
I
—
EP
—
FUNCTION
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to
AGNDS.
External Reference Input/Reference Buffer Decoupling. Bypass to AGNDS in close proximity with a
X5R or X7R 10µF 16V chip. See the Layout, Grounding, and Bypassing section.
Analog Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF
per PCB.
Positive Analog Input
Negative Analog Input. Connect AIN- to the analog ground plane or to a remote-sense ground.
Power-Supply Ground
Convert Start Input. The rising edge of CNVST initiates conversions. The falling edge of CNVST
with SCLK high enables the serial interface.
Serial Data Output. DOUT will change stated on the falling edge of SCLK.
Serial Clock Input. Clocks data out of the serial interface when the device is selected.
Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK.
Digital Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF
per PCB.
Analog Ground Sense. Zero current reference for the on-board DAC and reference source.
Reference for REFIO and REF.
Exposed Pad. EP is connected internally to GND. Connect to PCB GND.
www.maximintegrated.com
Maxim Integrated │  10