MAX1540A Datasheet, PDF (42/49 Pages) Maxim Integrated Products – Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
V_DDQ
V_CC
SKIP
DH1
10kΩ
LX1
REFIN1
DL1
10nF
10kΩ
MAX1541 GND
OD
GATE
FBLANK
CSP1
CSN1
OUT1
FB1
V_IN
C_IN
L
R_SENSE
C_OUT
V_TT = ^VDDQ
2
V_DDQ = DDR MEMORY SUPPLY VOLTAGE
V_TT = TERMINATION SUPPLY VOLTAGE
Figure 16. Active Bus Termination
Voltage Positioning
In applications where fast load transients occur, the out-
put voltage changes instantly by ESR_COUT x ΔI_LOAD.
Voltage positioning allows the use of fewer output
capacitors for such applications, and maximizes the out-
put voltage AC and DC tolerance window in tight-toler-
ance applications.
Figure 17 shows the connection of OUT_ and FB_ in
voltage-positioned and nonvoltage-positioned circuits.
In nonvoltage-positioned circuits, the MAX1540A/
MAX1541 regulate at the output capacitor. In voltage-
positioned circuits, the MAX1540A/MAX1541 regulate
on the inductor side of the current-sense resistor.
V_{OUT_} is reduced to:
V_OUT(VPS) = V_{OUT(NO LOAD)} - R_SENSE x I_LOAD
Figure 18 shows the voltage-positioning transient
response.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 19). If possible, mount all the power compo-
nents on the top side of the board, with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
• Minimize current-sensing errors by connecting
CSP_ and CSN_ directly across the current-sense
resistor (R_{SENSE_}).
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
• Route high-speed switching nodes (BST_, LX_,
DH_, and DL_) away from sensitive analog areas
(REF, FB_, CSP_, CSN_).
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (N_{L _} source, C_IN, C_OUT_, and D_L _
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite N_L _
and N_H_ in order to keep LX_, GND, DH_, and the
DL_ gate-drive lines short and wide. The DL_ and
DH_ gate traces must be short and wide (50 mils to
100 mils wide if the MOSFET is 1in from the con-
troller IC) to keep the driver impedance low and for
proper adaptive dead-time sensing.
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