MAX1540A Datasheet, PDF (30/49 Pages) Maxim Integrated Products – Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
POWER-GOOD
FAULT PROTECTION
0.9 x
INT REF_
1.1 x
0.7 x
INT REF_ INT REF_
1.16 x
INT REF_
INT FB_
20ms
TIMER
POR
FAULT
LATCH
ENABLE OVP
ENABLE UVP
*BLANK
FAULT
POWER-
GOOD
*MAIN MAX1541 CONTROLLER (OUT1) ONLY
Figure 9. Power-Good and Fault Protection
ON1 or ON2, or cycling V_CC power below 1V. For logic-
level output voltages, connect an external pullup resis-
tor between PGOOD_ and V_CC. A 100kΩ resistor works
well in most applications.
Note that the power-good window detectors are com-
pletely independent of the overvoltage and undervolt-
age-protection fault detectors.
Fault Blanking (MAX1541 FBLANK)
The main MAX1541 controller (OUT1) automatically
enters forced-PWM operation during all dynamic output-
voltage transitions (GATE transition detected) in order to
ensure fast, accurate transitions. FBLANK determines
how long the main MAX1541 controller maintains forced-
PWM operation (Table 6—typically 220µs (FBLANK =
V_CC), 140µs (FBLANK = open or GND), or 65µs
(FBLANK = REF).
When fault blanking is enabled (FBLANK = V_CC, open,
or REF), the MAX1541 also disables the overvoltage
and undervoltage fault protection for OUT1, and forces
PGOOD1 to a high-impedance state during the transi-
tion period selected by FBLANK (Table 6). This pre-
vents fault protection from latching off the MAX1541
and the PGOOD1 signal from going low when the out-
put voltage change (ΔV_OUT1) cannot occur as fast as
the REFIN1 voltage change (ΔV_REFIN1).
Table 6. FBLANK Configuration Table
FBLANK
V_CC
Open
REF
GND
OUT1 FAULT
BLANKING
Enabled
Enabled
Enabled
Disabled
FORCED-PWM
DURATION (MIN/TYP)
(µs)
120/220
80/140
35/65
80/140
Shutdown and Output Discharge (ON_)
When the output discharge mode is enabled (OVP/UVP
connected to V_CC or left open), and either ON_ is
pulled low or an OVP fault or thermal fault sets the fault
latch (Table 7), the controller discharges each output
through an internal 10Ω switch connected between
OUT_ and ground. While the output discharges, DL_ is
forced low and the PWM controller is disabled. Once
the output voltage drops below 0.3V, the low-side driver
pulls DL_ high, effectively clamping the output and LX_
switching node to ground. The reference remains active
until both output voltages are below 0.3V to provide an
accurate 0.3V discharge threshold.
When OVP/UVP is connected to REF or GND, the con-
troller does not actively discharge either output, and the
DL_ driver remains low until the system reenables the
controller. Under these conditions, the output discharge
rate is determined by the load current and output
capacitance.
The controller detects and latches the discharge-mode
state set by OVP/UVP on startup.
Fault Protection
The MAX1540A/MAX1541 provide over/undervoltage
fault protection (Figure 9). Drive OVP/UVP to enable
and disable fault protection as shown in Table 7. Once
activated, the controller continuously monitors the out-
put for undervoltage and overvoltage fault conditions.
Overvoltage Protection (OVP)
When the output voltage rises above 116% of the nomi-
nal regulation voltage and OVP is enabled (OVP/UVP =
V_CC or open), the OVP circuit sets the fault latch, shuts
down both the Quick-PWM controllers, immediately
pulls DH1 and DH2 low, and forces DL1 and DL2 high.
This turns on the synchronous-rectifier MOSFETs with
100% duty, rapidly discharging the output capacitors
and clamping both outputs to ground. Note that imme-
diately latching DL_ high can cause the output voltages
to go slightly negative due to energy stored in the out-
put LC at the instant the OV fault occurs. If the load
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